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    Semiconductor device
    1.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US5608236A

    公开(公告)日：1997-03-04

    申请号：US404465

    申请日：1995-03-15

    申请人： Hidetoshi Arakawa ,  Yoshitaka Sugawara ,  Masamitsu Inaba

    发明人： Hidetoshi Arakawa ,  Yoshitaka Sugawara ,  Masamitsu Inaba

    IPC分类号： H01L29/73 ,  H01L29/735 ,  H01L29/739 ,  H01L29/74 ,  H01L31/111

    CPC分类号： H01L29/7317 ,  H01L29/735 ,  H01L29/7393 ,  H01L29/7436

    摘要： A semiconductor device includes an emitter region, a collector region provided directly under the emitter region, and a two-region base structure. The first base region is interposed between the emitter and collector regions, and the second base region supports the collector region. The aforementioned regions have a progressively higher impurity concentrations, with the collector region having an impurity concentration higher than that of the first base region, the second base region having an impurity concentration higher than that of the collector region, and the emitter region having an impurity concentration higher than that of the base region. Also included is a resistance region formed, in one embodiment, from a projecting end portion of one of the base layers. The projecting end portion of the base is fabricated so that both base portions contact one another in the resistance region, and consequently both base portions are of the same potential. Electrodes are also provided for ohmicly contacting the emitter, collector, and base regions. The two-region base structure enables the device to achieve a high resistance, and thus to achieve simultaneously a high breakdown voltage and a high frequency (speed) characteristic.

    摘要翻译： 半导体器件包括发射极区域，直接位于发射极区域下方的集电极区域和两区域基极结构。 第一基极区域插在发射极和集电极区域之间，第二基极区域支撑集电极区域。 上述区域具有逐渐变高的杂质浓度，其中集电极区域的杂质浓度高于第一基极区域，第二基极区域的杂质浓度高于集电极区域的杂质浓度，发射极区域具有杂质 浓度高于基区。 还包括在一个实施例中由一个基底层的突出端部形成的电阻区域。 基座的突出端部被制造成使得两个基部在电阻区域中彼此接触，因此两个基部都具有相同的电位。 还提供电极用于欧姆接触发射极，集电极和基极区域。 双区域基础结构使得器件能够实现高电阻，从而同时实现高击穿电压和高频（速度）特性。

    Inverter apparatus comprising switching elements
    3.
    发明授权
    Inverter apparatus comprising switching elements 失效
    包括开关元件的逆变器装置

    公开(公告)号：US07570502B2

    公开(公告)日：2009-08-04

    申请号：US10565389

    申请日：2004-07-23

    申请人： Yoshitaka Sugawara ,  Katsunori Asano ,  Mitsuru Matsukawa ,  Yoshifumi Minowa ,  Toshihiko Shikata

    发明人： Yoshitaka Sugawara ,  Katsunori Asano ,  Mitsuru Matsukawa ,  Yoshifumi Minowa ,  Toshihiko Shikata

    IPC分类号： H02M7/5387

    CPC分类号： H02M7/521 ,  H02M1/32 ,  H02M1/38 ,  H02M2001/0012

    摘要： A problem to be solved by the present invention is to eliminate variation in potential in a turn-off time period of each GTO element, and to stabilize a gate drawing current by surely performing the turn-off of the GTO element. In an inverter apparatus having a three-phase inverter configured to include paired GTO elements an inverter control portion has a simultaneous switching prevention function of delaying a turn-on operation of each of the GTO elements which correspond to phases other than a phase corresponding to an optional one of the GTO elements and also correspond to an electrode opposite to an electrode corresponding to the optional one of the GTO elements by a predetermined time in a case where a turn-on command signal for turning on each of the GTO elements is generated within a predetermined time period since the turn-off of the optional one of the GTO elements.

    摘要翻译： 本发明要解决的问题是消除每个GTO元件的关断时间段中的电位变化，并且通过可靠地执行GTO元件的关断来稳定栅极引出电流。 在具有配置为包括成对的GTO元件的三相逆变器的逆变器装置中，逆变器控制部具有同时切换防止功能，其延迟对应于除了相应于相同的相位之外的相位的每个GTO元件的接通操作 在GTO元件中可选的一个，并且在用于接通每个GTO元件的接通命令信号的情况下，也对应于与对应于GTO元件中的任选一个GTO元件的电极相对预定时间的电极 自从关闭任选的一个GTO元件以来的预定时间段。

    Silicon-containing curing composition and heat cured product thereof
    5.
    发明申请
    Silicon-containing curing composition and heat cured product thereof 有权
    含硅固化组合物及其热固化产物

    公开(公告)号：US20070197755A1

    公开(公告)日：2007-08-23

    申请号：US10594221

    申请日：2005-05-10

    申请人： Takashi Sueyoshi ,  Ken-ichiro Hiwatari ,  Tadashi Janado ,  Yoshikazu Shoji ,  Yoshitaka Sugawara

    发明人： Takashi Sueyoshi ,  Ken-ichiro Hiwatari ,  Tadashi Janado ,  Yoshikazu Shoji ,  Yoshitaka Sugawara

    IPC分类号： C08L83/04 ,  C08G77/04

    CPC分类号： C08L83/04 ,  C08G77/12 ,  C08G77/14 ,  C08G77/18 ,  C08G77/20 ,  C08G77/70 ,  C08L83/00

    摘要： A curable composition which comprises at least one of the following (A), (B), and (C) and further contains the following (D) (provided that when (C) is not contained, both (A) and (B) are contained). (A): A silicon-containing polymer in which the content of components having a weight-average molecular weight of 1,000 or lower is 20 wt. % or lower and which has a reactive group A′ and one or more Si—O—Si bonds. (B): A silicon-containing polymer in which the content of components having a weight-average molecular weight of 1,000 or lower is 20 wt. % or lower and which has an Si—H group and one or more Si—O—Si bonds. (C): A silicon-containing polymer in which the content of components having a weight-average molecular weight of 1,000 or lower is 20 wt. % or lower and which has a reactive group A′, an Si—H group, and one or more Si—O—Si bonds. (D): A catalyst for curing reaction which is a platinum catalyst. The reactive group A′ is any of Si—R1, Si—O—R2, and Si—R3—OCOC(R4)═CH2, provided that R1 and R2 each is alkenyl, R3 is alkylene and/or arylene, and R4 is hydrogen or methyl.

    摘要翻译： 包含以下（A），（B）和（C）中的至少一个的可固化组合物，并且还包含以下（D）（前提是不含（C）时，（A）和（B） 被包含）。 （A）：重均分子量为1000以下的成分的含量为20重量％的含硅聚合物。 ％以下，具有反应性基团A'和一个或多个Si-O-Si键。 （B）：重均分子量为1000以下的成分的含量为20重量％的含硅聚合物。 ％以下，并且具有Si-H基和一个或多个Si-O-Si键。 （C）：重均分子量为1000以下的成分的含量为20重量％的含硅聚合物。 ％以下，具有反应性基团A'，Si-H基和一个或多个Si-O-Si键。 （D）：铂催化剂用于固化反应的催化剂。 反应性基团A'是Si-R 1，Si-OR 2和Si-R 3 -OCOC（R SUP）中的任何一种 > 4 ） - CH 2，条件是R 1和R 2各自为烯基，R 3， SUP>是亚烷基和/或亚芳基，R 4是氢或甲基。

    Voltage-driven type semiconductor device
    8.
    发明授权
    Voltage-driven type semiconductor device 失效
    电压驱动型半导体器件

    公开(公告)号：US5572048A

    公开(公告)日：1996-11-05

    申请号：US153047

    申请日：1993-11-17

    申请人： Yoshitaka Sugawara

    发明人： Yoshitaka Sugawara

    IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L27/07 ,  H01L29/739 ,  H01L29/74 ,  H01L29/744 ,  H01L29/78 ,  H01L31/111

    CPC分类号： H01L27/0722 ,  H01L27/0716 ,  H01L29/7393 ,  H01L29/7395

    摘要： According to the present invention, a MOSFET is formed of an n source, a p well, an n drain and a MOS gate electrode, a bipolar transistor is formed of an n emitter, a p base and an n collector formed in sequential order adjacent to the n drain. These transistors are formed by being merged with each other by the contact of n drain and the n emitter of the same conductivity type. Holes are injected into the drain of a voltage-driven type transistor comprised of the MOSFET from the bipolar transistor having a very small collector saturation resistance. With this, it is possible to give rise to conductivity modulation in the drain of the MOSFET, while the power dissipation of the voltage-driven type semiconductor device becomes very small.

    摘要翻译： 根据本发明，MOSFET由n个源极，p阱，n沟道和MOS栅极形成，双极晶体管由n个发射极，ap基极和n个集电极形成，其邻接于 排水 这些晶体管通过n沟道和相同导电类型的n发射极的接触而彼此合并而形成。 孔被注入到由具有非常小的集电极饱和电阻的双极晶体管的MOSFET构成的电压驱动型晶体管的漏极中。 由此，可以在MOSFET的漏极中引起电导率调制，而电压驱动型半导体器件的功耗变得非常小。

    Semiconductor device having a semi-insulating layer
    9.
    发明授权
    Semiconductor device having a semi-insulating layer 失效
    具有半绝缘层的半导体器件

    公开(公告)号：US5552625A

    公开(公告)日：1996-09-03

    申请号：US208138

    申请日：1994-03-09

    申请人： Susumu Murakami ,  Takuya Fukuda ,  Yoshiteru Shimizu ,  Yoshitaka Sugawara

    发明人： Susumu Murakami ,  Takuya Fukuda ,  Yoshiteru Shimizu ,  Yoshitaka Sugawara

    IPC分类号： H01L29/06 ,  H01L29/40

    CPC分类号： H01L29/404 ,  H01L29/0626 ,  H01L29/408

    摘要： A semiconductor device has a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type contacted by respective first and second electrodes. A semi-insulating layer extends between the first and second electrodes and there is a first insulating layer between the semi-insulating layer and the first semiconductor region. The sheet resistivity of the semi-insulating layer varies, and this improves the high breakdown voltage of the p-n junction of the semiconductor device between the first and second semiconductor layers, by acting as a shield for charges included on a passivation insulation layer covering the semi-insulating layer and the first and second electrodes. Third semiconductor regions, with corresponding third electrodes, extend around, and are spaced from, the second semiconductor region. The third electrodes extend over the parts of the first semiconductor region adjacent the third semiconductor regions, and this also serve to improve the breakdown voltage. The second electrode may also extend over the part of the first semiconductor region adjacent the second semiconductor region to cover the p-n junction therebetween.

    摘要翻译： 半导体器件具有第一导电类型的第一半导体区域和与第一和第二电极接触的第二导电类型的第二半导体区域。 半绝缘层在第一和第二电极之间延伸，并且在半绝缘层和第一半导体区之间存在第一绝缘层。 半绝缘层的薄层电阻率变化，这通过充当覆盖半导体层的钝化绝缘层上的电荷的屏蔽来改善第一和第二半导体层之间的半导体器件的pn结的高击穿电压 绝缘层和第一和第二电极。 具有对应的第三电极的第三半导体区域围绕第二半导体区域延伸并且与第二半导体区域间隔开。 第三电极在与第三半导体区域相邻的第一半导体区域的部分上延伸，这也用于提高击穿电压。 第二电极还可以在与第二半导体区域相邻的第一半导体区域的部分上延伸以覆盖它们之间的p-n结。

    Semiconductor device
    10.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US4419685A

    公开(公告)日：1983-12-06

    申请号：US245510

    申请日：1981-03-19

    申请人： Yoshitaka Sugawara ,  Tatsuya Kamei ,  Tetsuma Sakurai

    发明人： Yoshitaka Sugawara ,  Tatsuya Kamei ,  Tetsuma Sakurai

    IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L29/735

    CPC分类号： H01L29/402 ,  H01L29/0821 ,  H01L29/41708 ,  H01L29/735

    摘要： A lateral transistor having a high breakdown voltage and operable with an improved current amplification factor and an improved cut-off frequency comprises in a semiconductor substrate of one conductivity type, a base layer of the one conductivity type and an emitter layer of the other conductivity type formed in the base layer. A first collector layer of the other conductivity type is formed in the one principal surface of the substrate apart from the base layer and a second collector layer of the same conductivity type having an impurity concentration lower than that of the first collector layer is formed between the first collector layer and the base layer in contact with the latter layers. Emitter, base and collector electrodes make ohmic contact with the emitter, base and first collector layers respectively. The emitter electrode extends on a passivation film covering the one principal surface of the substrate to terminate at a point on the second collector layer.

    摘要翻译： 具有高击穿电压并且具有改善的电流放大因子和改进的截止频率的横向晶体管包括在一种导电类型的半导体衬底中，一种导电类型的基极层和另一种导电类型的发射极层 形成在基层。 另外导电型的第一集电体层形成在与基底层相隔的基板的一个主表面上，并且在第二集电极层之间形成具有比第一集电体层低的杂质浓度的相同导电类型的第二集电极层 第一集电体层和与后一层接触的基层。 发射极，基极和集电极电极分别与发射极，基极和第一集电极层欧姆接触。 发射电极在覆盖衬底的一个主表面的钝化膜上延伸以终止于第二集电极层上的一点。