公开(公告)号：US20090194321A1

公开(公告)日：2009-08-06

申请号：US12356106

申请日：2009-01-20

申请人： Yasuto Ishimaru ,  Hirofumi Ebe

发明人： Yasuto Ishimaru ,  Hirofumi Ebe

IPC分类号： H05K1/18 ,  H05K3/10

CPC分类号： H05K1/0209 ,  H01L23/3735 ,  H01L23/562 ,  H01L2224/16225 ,  H05K1/0271 ,  H05K1/189 ,  H05K2201/09318 ,  H05K2201/0969 ,  H05K2201/09781 ,  H05K2201/10674

摘要： A mounting region is provided at an approximately center of one surface of an insulating layer. A conductive trace is formed so as to outwardly extend from inside of the mounting region. A cover insulating layer is formed in a periphery of the mounting region so as to cover the conductive trace. A terminal of the conductive trace is arranged in the mounting region, and a bump of an electronic component is bonded to the terminal. A metal layer made of copper, for example, is provided on the other surface of the insulating layer. A pair of slits is formed in the metal layer such that a region being opposite to the electronic component is sandwiched therebetween. Each slit is formed so as not to divide the metal layer into a plurality of regions.

摘要翻译： 安装区域设置在绝缘层的一个表面的大致中心处。 导电迹线形成为从安装区域的内部向外延伸。 在安装区域的周围形成覆盖绝缘层以覆盖导电迹线。 导电迹线的端子布置在安装区域中，并且电子部件的凸块接合到端子。 例如，在绝缘层的另一个表面上设置由铜构成的金属层。 在金属层中形成一对狭缝，使得与电子部件相对的区域夹在其间。 每个狭缝形成为不将金属层划分成多个区域。

公开(公告)号：US08581110B2

公开(公告)日：2013-11-12

申请号：US12356106

申请日：2009-01-20

申请人： Yasuto Ishimaru ,  Hirofumi Ebe

发明人： Yasuto Ishimaru ,  Hirofumi Ebe

IPC分类号： H05K1/18

CPC分类号： H05K1/0209 ,  H01L23/3735 ,  H01L23/562 ,  H01L2224/16225 ,  H05K1/0271 ,  H05K1/189 ,  H05K2201/09318 ,  H05K2201/0969 ,  H05K2201/09781 ,  H05K2201/10674

摘要： A mounting region is provided at an approximately center of one surface of an insulating layer. A conductive trace is formed so as to outwardly extend from inside of the mounting region. A cover insulating layer is formed in a periphery of the mounting region so as to cover the conductive trace. A terminal of the conductive trace is arranged in the mounting region, and a bump of an electronic component is bonded to the terminal. A metal layer made of copper, for example, is provided on the other surface of the insulating layer. A pair of slits is formed in the metal layer such that a region being opposite to the electronic component is sandwiched therebetween. Each slit is formed so as not to divide the metal layer into a plurality of regions.

摘要翻译： 安装区域设置在绝缘层的一个表面的大致中心处。 导电迹线形成为从安装区域的内部向外延伸。 在安装区域的周围形成覆盖绝缘层以覆盖导电迹线。 导电迹线的端子布置在安装区域中，并且电子部件的凸块接合到端子。 例如，在绝缘层的另一个表面上设置由铜构成的金属层。 在金属层中形成一对狭缝，使得与电子部件相对的区域夹在其间。 每个狭缝形成为不将金属层划分成多个区域。

公开(公告)号：US08354599B2

公开(公告)日：2013-01-15

申请号：US12163062

申请日：2008-06-27

申请人： Hirofumi Ebe ,  Yasuto Ishimaru

发明人： Hirofumi Ebe ,  Yasuto Ishimaru

IPC分类号： H05K1/11

CPC分类号： H05K1/111 ,  H01L2224/16225 ,  H05K3/3436 ,  H05K3/3442 ,  H05K3/3473 ,  H05K2201/09381 ,  H05K2201/09427 ,  H05K2201/09727 ,  H05K2201/10674 ,  Y02P70/611 ,  Y02P70/613

摘要： Each wiring pattern is composed of a conductor layer and a tin plating layer, and includes a tip portion, a connection portion and a signal transmission portion. The width of the tip portion is equal to the width of the signal transmission portion, and the width of the connection portion is smaller than the widths of the tip portion and the signal transmission portion. The connection portions of wiring patterns and bumps of an electronic component are connected to one another, respectively, by heat-sealing when the electronic component is mounted. Respective distances A1, A2 are set to not less than 0.5 μm. Respective distances B1, B2 are set to not less than 20 μm. The thickness of the tin plating layer is set to not less than 0.07 μm and not more than 0.25 μm.

摘要翻译： 每个布线图案由导体层和镀锡层组成，并且包括尖端部分，连接部分和信号传输部分。 前端部分的宽度等于信号传输部分的宽度，连接部分的宽度小于前端部分和信号传输部分的宽度。 电子部件的布线图案和凸块的连接部分分别通过在安装电子部件时进行热封而相互连接。 各距离A1，A2设定为不小于0.5μm。 各距离B1，B2设定为20μm以上。 镀锡层的厚度设定为0.07μm以上且0.25μm以下。

公开(公告)号：US08102664B2

公开(公告)日：2012-01-24

申请号：US12357714

申请日：2009-01-22

申请人： Yasuto Ishimaru ,  Hirofumi Ebe

发明人： Yasuto Ishimaru ,  Hirofumi Ebe

IPC分类号： H05K1/18

CPC分类号： H05K3/303 ,  H01L23/3735 ,  H01L2224/16225 ,  H05K1/0203 ,  H05K1/0269 ,  H05K1/189 ,  H05K2201/0108 ,  H05K2201/09318 ,  H05K2201/0969 ,  H05K2201/09781 ,  H05K2201/10674 ,  H05K2203/166 ,  Y02P70/613 ,  Y10T29/49162

摘要： A mounting region having a rectangular shape is provided at an approximately center of one surface of an insulating layer. A plurality of conductive traces are formed so as to outwardly extend from the inside of the mounting region. A cover insulating layer is formed so as to cover the plurality of conductive traces in a periphery of the mounting region. An electronic component is mounted on the insulating layer so as to overlap with the mounting region. A metal layer is provided on the other surface of the insulating layer. Openings having a rectangular shape are formed in the metal layer along a pair of longer sides and a pair of shorter sides of the mounting region. The openings are opposite to part of terminals of the plurality of conductive traces, respectively, with the insulating layer sandwiched therebetween.

摘要翻译： 在绝缘层的一个表面的大致中心处设置具有矩形形状的安装区域。 多个导电迹线被形成为从安装区域的内部向外延伸。 形成覆盖绝缘层，以覆盖安装区域周边的多个导电迹线。 电子部件安装在绝缘层上以与安装区域重叠。 在绝缘层的另一个表面上设置金属层。 沿着一对长边和安装区域的一对短边在金属层中形成具有矩形形状的开口。 开口分别与多个导电迹线的端子的一部分相对，绝缘层夹在其间。

公开(公告)号：US08022306B2

公开(公告)日：2011-09-20

申请号：US12426404

申请日：2009-04-20

申请人： Hirofumi Ebe ,  Yasuto Ishimaru

发明人： Hirofumi Ebe ,  Yasuto Ishimaru

IPC分类号： H05K1/09 ,  B05D5/12

CPC分类号： H05K1/0271 ,  H01L23/3735 ,  H01L23/49838 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K1/0209 ,  H05K1/189 ,  H05K2201/09663 ,  H05K2201/09781 ,  H05K2201/10674

摘要： A mounting region is provided at a substantially center of one surface of an insulating layer. A metal layer is provided on the other surface of the insulating layer. A slit is formed to cross a region (an opposite region) of the metal layer that coincides with the mounting region and to divide the metal layer. A plurality of regions (large regions) of the metal layer divided by the slit each include a partial region (small region) of the opposite region. The area of each large region is set corresponding to the area of the small region included therein. Specifically, the small region having the area of A [%] with respect to the whole area of the opposite region is included in the large region having the area of (A±δ) [%] with respect to the whole area of the metal layer. Here, δ is an acceptable error range, and the acceptable error range δ is not more than (A×0.3).

摘要翻译： 安装区域设置在绝缘层的一个表面的大致中心处。 在绝缘层的另一个表面上设置金属层。 形成狭缝以与金属层的与安装区域重合的区域（相对区域）交叉并分割金属层。 由狭缝分割的金属层的多个区域（大区域）各自包括相对区域的部分区域（小区域）。 每个大区域的面积对应于其中包括的小区域的面积。 具体而言，相对于金属的整个面积，面积为（A±δ）[％]的面积相对于相对区域的整个面积的面积为A [％]的小区域被包括 层。 这里，δ是可接受的误差范围，可接受的误差范围δ不大于（A×0.3）。

公开(公告)号：US20090195997A1

公开(公告)日：2009-08-06

申请号：US12356099

申请日：2009-01-20

申请人： Yasuto Ishimaru ,  Hirofumi Ebe

发明人： Yasuto Ishimaru ,  Hirofumi Ebe

IPC分类号： H05K1/18 ,  H05K3/10

CPC分类号： H05K1/0209 ,  H01L23/3735 ,  H01L23/562 ,  H01L2224/16225 ,  H05K1/0271 ,  H05K1/189 ,  H05K2201/09318 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2201/09781 ,  H05K2201/10674 ,  Y10T29/49162

摘要： A mounting region is provided at an approximately center of one surface of an insulating layer. A conductive trace is formed so as to outwardly extend from inside of the mounting region. A cover insulating layer is formed in the periphery of the mounting region so as to cover the conductive trace. A terminal of the conductive trace is arranged in the mounting region, and a bump of an electronic component is bonded to the terminal. A metal layer made of copper, for example, is provided on the other surface of the insulating layer. A slit is formed in the metal layer so as to cross a region being opposite to the electronic component and to divide the metal layer.

摘要翻译： 安装区域设置在绝缘层的一个表面的大致中心处。 导电迹线形成为从安装区域的内部向外延伸。 在安装区域的周围形成覆盖绝缘层以覆盖导电迹线。 导电迹线的端子布置在安装区域中，并且电子部件的凸块接合到端子。 例如，在绝缘层的另一个表面上设置由铜构成的金属层。 在金属层中形成狭缝，以跨越与电子部件相对的区域并分割金属层。

公开(公告)号：US08097814B2

公开(公告)日：2012-01-17

申请号：US12356099

申请日：2009-01-20

申请人： Yasuto Ishimaru ,  Hirofumi Ebe

发明人： Yasuto Ishimaru ,  Hirofumi Ebe

IPC分类号： H05K1/16

CPC分类号： H05K1/0209 ,  H01L23/3735 ,  H01L23/562 ,  H01L2224/16225 ,  H05K1/0271 ,  H05K1/189 ,  H05K2201/09318 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2201/09781 ,  H05K2201/10674 ,  Y10T29/49162

摘要： A mounting region is provided at an approximately center of one surface of an insulating layer. A conductive trace is formed so as to outwardly extend from inside of the mounting region. A cover insulating layer is formed in the periphery of the mounting region so as to cover the conductive trace. A terminal of the conductive trace is arranged in the mounting region, and a bump of an electronic component is bonded to the terminal. A metal layer made of copper, for example, is provided on the other surface of the insulating layer. A slit is formed in the metal layer so as to cross a region being opposite to the electronic component and to divide the metal layer.

摘要翻译： 安装区域设置在绝缘层的一个表面的大致中心处。 导电迹线形成为从安装区域的内部向外延伸。 在安装区域的周围形成覆盖绝缘层以覆盖导电迹线。 导电迹线的端子布置在安装区域中，并且电子部件的凸块接合到端子。 例如，在绝缘层的另一个表面上设置由铜构成的金属层。 在金属层中形成狭缝，以跨越与电子部件相对的区域并分割金属层。

公开(公告)号：US07659605B2

公开(公告)日：2010-02-09

申请号：US12232883

申请日：2008-09-25

申请人： Yasuto Ishimaru ,  Hirofumi Ebe

发明人： Yasuto Ishimaru ,  Hirofumi Ebe

IPC分类号： H01L23/495

CPC分类号： H05K1/111 ,  H01L23/49838 ,  H01L23/4985 ,  H01L2924/0002 ,  H05K1/056 ,  H05K1/189 ,  H05K2201/09709 ,  H05K2201/09781 ,  H05K2201/10674 ,  H05K2203/1545 ,  Y02P70/611 ,  H01L2924/00

摘要： A COF board includes an insulating layer, and a terminal portion formed on the insulating layer. The terminal portion includes a first lead extending in a longitudinal direction, and a second lead extending in the longitudinal direction, and having a smaller length in the longitudinal direction than a length of the first lead in the longitudinal direction. The first leads are arranged in spaced-apart relation in a direction perpendicular to the longitudinal direction. The second leads are arranged in the direction perpendicular to the longitudinal direction to be interposed between the mutually adjacent first leads such that, when the mutually adjacent first leads are projected in an adjacent direction thereof, overlap portions where the second leads overlap with the first leads and non-overlap portions where the second leads do not overlap with the first leads are formed. Dummy leads are provided at the non-overlap portions.

摘要翻译： COF板包括绝缘层和形成在绝缘层上的端子部分。 端子部分包括沿纵向方向延伸的第一引线和沿纵向方向延伸的第二引线，并且在纵向方向上的长度比第一引线在纵向方向上的长度更小。 第一引线在垂直于纵向方向的方向上以间隔的关系布置。 第二引线沿垂直于纵向方向的方向布置以插入在相互相邻的第一引线之间，使得当相互相邻的第一引线沿其相邻方向突出时，第二引线与第一引线重叠的重叠部分 并且形成第二引线不与第一引线重叠的非重叠部分。 在非重叠部分提供虚拟引线。

公开(公告)号：US20090096069A1

公开(公告)日：2009-04-16

申请号：US12232883

申请日：2008-09-25

申请人： Yasuto Ishimaru ,  Hirofumi Ebe

发明人： Yasuto Ishimaru ,  Hirofumi Ebe

IPC分类号： H01L23/495

CPC分类号： H05K1/111 ,  H01L23/49838 ,  H01L23/4985 ,  H01L2924/0002 ,  H05K1/056 ,  H05K1/189 ,  H05K2201/09709 ,  H05K2201/09781 ,  H05K2201/10674 ,  H05K2203/1545 ,  Y02P70/611 ,  H01L2924/00

摘要： A COF board includes an insulating layer, and a terminal portion formed on the insulating layer. The terminal portion includes a first lead extending in a longitudinal direction, and a second lead extending in the longitudinal direction, and having a smaller length in the longitudinal direction than a length of the first lead in the longitudinal direction. The first leads are arranged in spaced-apart relation in a direction perpendicular to the longitudinal direction. The second leads are arranged in the direction perpendicular to the longitudinal direction to be interposed between the mutually adjacent first leads such that, when the mutually adjacent first leads are projected in an adjacent direction thereof, overlap portions where the second leads overlap with the first leads and non-overlap portions where the second leads do not overlap with the first leads are formed. Dummy leads are provided at the non-overlap portions.

摘要翻译： COF板包括绝缘层和形成在绝缘层上的端子部分。 端子部分包括沿纵向方向延伸的第一引线和沿纵向方向延伸的第二引线，并且在纵向方向上的长度比第一引线在纵向方向上的长度更小。 第一引线在垂直于纵向方向的方向上以间隔的关系布置。 第二引线沿垂直于纵向方向的方向布置以插入在相互相邻的第一引线之间，使得当相互相邻的第一引线沿其相邻方向突出时，第二引线与第一引线重叠的重叠部分 并且形成第二引线不与第一引线重叠的非重叠部分。 在非重叠部分提供虚拟引线。

公开(公告)号：US08822048B2

公开(公告)日：2014-09-02

申请号：US13356955

申请日：2012-01-24

申请人： Hirofumi Ebe ,  Shinichi Inoue ,  Yoshihiro Furukawa

发明人： Hirofumi Ebe ,  Shinichi Inoue ,  Yoshihiro Furukawa

IPC分类号： H01M2/02 ,  H01M14/00 ,  H05K5/03 ,  B32B33/00

CPC分类号： C08K5/3475 ,  H01M8/00 ,  H01M10/0525 ,  H01M10/4257 ,  H05K1/0393 ,  H05K3/247 ,  H05K2203/122

摘要： A conductor layer is formed on one surface of a base insulating layer. The conductor layer includes a collector portion, and a drawn-out conductor portion extending in an elongated shape from the collector portion. A cover layer is formed on the base insulating layer to cover a predetermined portion of the conductor layer. A material for the cover layer includes a paste composition containing a compound expressed by the formula (1).

摘要翻译： 在基底绝缘层的一个表面上形成导体层。 导体层包括集电器部分和从收集器部分延伸成细长形状的拉出导体部分。 覆盖层形成在基底绝缘层上以覆盖导体层的预定部分。 用于覆盖层的材料包括含有由式（1）表示的化合物的糊剂组合物。