公开(公告)号：US5499207A

公开(公告)日：1996-03-12

申请号：US281568

申请日：1994-07-28

申请人： Hiroshi Miki ,  Yuzuru Ohji ,  Shinichi Tachi

发明人： Hiroshi Miki ,  Yuzuru Ohji ,  Shinichi Tachi

IPC分类号： H01L21/02 ,  H01L27/108 ,  G11C11/24

CPC分类号： H01L28/55 ,  H01L27/10817 ,  H01L28/60 ,  Y10S438/974

摘要： With recent decreases in the size of semiconductor memories, isolation problems typically arise during fabrication of a capacitor for a high-capacity semiconductor memory device. To overcome this, arrangements are provided to improve the isolation between capacitor elements even if those elements are extremely close together. For example, if a material such as platinum is used as a capacitor bottom electrode, a thin layer of titanium oxide can be deposited before forming the platinum, to provide a structure in which the titanium oxide is on the bottom portion of the trench. A high-dielectric-constant insulator is then formed over that structure by the Chemical Vapor Deposition. The high-dielectric-constant insulator has a composition which satisfies the stoichiometric composition over the platinum and which has more titanium atoms than those of the stoichiometric composition on the trench bottom. The resulting non-stoichiometric composition layer formed on the trench bottom has a low dielectric constant and a high insulation to maintain electric insulation between adjoining bottom capacitor electrodes. Because of a low crystallization, moreover, a layer having a planarized morphology is formed.

摘要翻译： 随着半导体存储器的尺寸近来的减小，在大容量半导体存储器件的电容器制造过程中通常会出现隔离问题。 为了克服这一点，即使这些元件非常靠近在一起，也提供了用于改善电容器元件之间的隔离的布置。 例如，如果使用诸如铂的材料作为电容器底部电极，则可以在形成铂之前沉积氧化钛薄层，以提供氧化钛在沟槽的底部上的结构。 然后通过化学气相沉积在该结构上形成高介电常数绝缘体。 高介电常数绝缘体具有满足铂的化学计量组成并且具有比沟槽底部的化学计量组成更多的钛原子的组成。 形成在沟槽底部上的非化学计量组合物层具有低介电常数和高绝缘性，以保持邻接的底部电容器电极之间的电绝缘。 此外，由于低结晶，形成具有平坦化形态的层。

公开(公告)号：US5343353A

公开(公告)日：1994-08-30

申请号：US929918

申请日：1992-08-17

申请人： Hiroshi Miki ,  Yuzuru Ohji ,  Shinichi Tachi ,  Keiichi Kanehori

发明人： Hiroshi Miki ,  Yuzuru Ohji ,  Shinichi Tachi ,  Keiichi Kanehori

IPC分类号： H01L27/10 ,  C23C16/40 ,  H01L21/02 ,  H01L21/314 ,  H01L21/316 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108 ,  H01G4/10 ,  B05D5/12 ,  H01G7/00

CPC分类号： H01L28/56 ,  C23C16/409 ,  H01L21/31691 ,  Y10T29/435

摘要： A microminiature, large capacitor for a semiconductor memory is formed from a raw material compound of plural different kinds of metal atoms for deposition, irrespective of the material, temperature and surface condition of a substrate, thereby forming a thin dielectric film having uniform characteristics not affected by the interface even though the film is made as thin as approximately 0.1 .mu.m. The microminiature large capacitance capacitor has a capacitance unaffected by an oxide existing at the interface between a ferroelectric and electrodes without using precious metals such as platinum having the least degree of freedom in deposition of thin films and microminiature processing. The ferroelectric thin film is deposited using an organic metal comprising a plurality of kinds of metal elements in conformity with the composition of a desired dielectric. As electrodes for use in forming a capacitor, a substance exhibiting conductivity after oxidation is preferably employed.

摘要翻译： 用于半导体存储器的微型大电容器由用于沉积的多种不同种类的金属原子的原料化合物形成，与基板的材料，温度和表面状况无关，从而形成具有不受影响的均匀特性的薄电介质膜 通过界面即使薄膜制成薄约0.1μm。 微型大容量电容器具有不受在铁电体和电极之间的界面处存在的氧化物的影响，而不使用贵金属如铂，其沉积薄膜和微型加工具有最小的自由度。 使用包含多种金属元素的有机金属，使其与所需电介质的组成一致地沉积铁电薄膜。 作为用于形成电容器的电极，优选使用氧化后显示导电性的物质。

公开(公告)号：US5736449A

公开(公告)日：1998-04-07

申请号：US592464

申请日：1996-01-26

申请人： Hiroshi Miki ,  Yuzuru Ohji ,  Shinichi Tachi

发明人： Hiroshi Miki ,  Yuzuru Ohji ,  Shinichi Tachi

IPC分类号： H01L21/02 ,  H01L27/108 ,  H01L21/20

CPC分类号： H01L28/55 ,  H01L27/10817 ,  H01L28/60 ,  Y10S438/974

摘要： With recent decreases in the size of semiconductor memories, isolation problems typically arise during fabrication of a capacitor for a high-capacity semiconductor memory device. To overcome this, arrangements are provided to improve the isolation between capacitor elements even if those elements are extremely close together. For example, if a material such as platinum is used as a capacitor bottom electrode, a thin layer of titanium oxide can be deposited before forming the platinum, to provide a structure in which the titanium oxide is on the bottom portion of the trench. A high-dielectric-constant insulator is then formed over that structure by the Chemical Vapor Deposition. The high-dielectric-constant insulator has a composition which satisfies the stoichiometric composition over the platinum and which has more titanium atoms than those of the stoichiometric composition on the trench bottom. The resulting non-stoichiometric composition layer formed on the trench bottom has a low dielectric constant and a high insulation to maintain electric insulation between adjoining bottom capacitor electrodes. Because of a low crystallization, moreover, a layer having a planarized morphology is formed.

公开(公告)号：US20120097533A1

公开(公告)日：2012-04-26

申请号：US13316927

申请日：2011-12-12

申请人： Shuji NOMURA ,  Ayumu Miyoshi ,  Hiroshi Miki

发明人： Shuji NOMURA ,  Ayumu Miyoshi ,  Hiroshi Miki

IPC分类号： C23C14/34

CPC分类号： C23C14/3464

摘要： A sputtering apparatus including a target holder configured to hold at least two targets; a substrate holder configured to hold a substrate; a first shutter plate arranged between the target holder and the substrate holder, the first shutter plate having at least two holes and being capable of rotating around an axis; a second shutter plate arranged between the first shutter plate and the substrate holder, the second shutter plate having at least two holes and being capable of rotating around the axis; wherein the first and second shutter plates are rotated such that paths are simultaneously created between the at least two targets and the substrate through the at least two holes of the rotated first shutter plate and the at least two holes of the rotated second shutter plate, and a film is formed on the substrate by co-sputtering of the at least two targets.

摘要翻译： 一种溅射装置，包括被配置为保持至少两个靶的目标支架; 衬底保持器，其构造成保持衬底; 布置在所述目标保持器和所述基板保持器之间的第一挡板，所述第一挡板具有至少两个孔并且能够绕轴线旋转; 布置在所述第一活门板和所述衬底支架之间的第二活门板，所述第二活门板具有至少两个孔并能绕所述轴线旋转; 其中所述第一和第二快门板旋转，使得通过旋转的第一快门板的至少两个孔和旋转的第二快门板的至少两个孔同时在至少两个目标和基板之间产生通路，以及 通过共溅射至少两个靶，在衬底上形成膜。

公开(公告)号：US20070228427A1

公开(公告)日：2007-10-04

申请号：US11723683

申请日：2007-03-21

申请人： Yuichi Matsui ,  Hiroshi Miki

发明人： Yuichi Matsui ,  Hiroshi Miki

IPC分类号： H01L29/76

CPC分类号： H01L27/10852 ,  H01L21/02175 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/31641 ,  H01L21/31645 ,  H01L27/10814 ,  H01L27/10894 ,  H01L28/91

摘要： HfO2 films and ZrO2 films are currently being developed for use as capacitor dielectric films in 85 nm technology node DRAM. However, these films will be difficult to use in 65 nm technology node or later DRAM, since they have a relative dielectric constant of only 20-25. The dielectric constant of such films may be increased by stabilizing their cubic phase. However, this results in an increase in the leakage current along the crystal grain boundaries, which makes it difficult to use these films as capacitor dielectric films. To overcome this problem, the present invention dopes a base material of HfO2 or ZrO2 with an oxide of an element having a large ion radius, such as Y or La, to increase the oxygen coordination number of the base material and thereby increase its relative dielectric constant to 30 or higher even when the base material is in its amorphous state. Thus, the present invention provides dielectric films that can be used to form DRAM capacitors that meet the 65 nm technology node or later.

摘要翻译： 目前正在开发用于85nm技术节点DRAM中的电容器电介质膜的HfO 2膜和ZrO 2膜。 然而，这些膜将难以在65nm技术节点或之后的DRAM中使用，因为它们的相对介电常数只有20-25。 这些膜的介电常数可以通过稳定它们的立方相来增加。 然而，这导致沿着晶粒边界的漏电流的增加，这使得难以将这些膜用作电容器电介质膜。 为了克服这个问题，本发明将HfO 2 2或ZrO 2 2的基材与具有大离子半径的元素的氧化物如Y或La掺杂， 以增加基材的氧配位数，从而即使当基材处于非晶状态时，其相对介电常数也提高到30以上。 因此，本发明提供可用于形成满足65nm技术节点或更高版本的DRAM电容器的电介质膜。

公开(公告)号：US07034355B2

公开(公告)日：2006-04-25

申请号：US10496000

申请日：2002-12-02

申请人： Hiroshi Miki

发明人： Hiroshi Miki

IPC分类号： H01L29/76

CPC分类号： H01L21/28211 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/511

摘要： To achieve a higher operating speed, higher reliability, and lower power consumption by reducing the thickness of an inter-poly silicon insulator film between a floating gate and a control gate of a flash memory, a silicon dioxide film, a silicon nitride film, tantalum pentoxide, and a silicon dioxide film are formed in a multilayer structure to serve as the inter-poly insulator film between a floating gate and a control gate. With this configuration, tantalum pentoxide formed on the silicon nitride film has a dielectric constant of 50 or more, which is higher than that of the silicon dioxide film, and the thickness of the inter-poly silicon insulator film can be reduced.

摘要翻译： 为了通过减小​​浮动栅极和闪速存储器的控制栅极之间的多晶硅绝缘膜的厚度来实现更高的操作速度，更高的可靠性和更低的功率消耗，二氧化硅膜，氮化硅膜，钽 五氧化物和二氧化硅膜形成为多层结构，以用作浮置栅极和控制栅极之间的多晶硅绝缘膜。 利用这种构造，形成在氮化硅膜上的五氧化二钽的介电常数为50以上，高于二氧化硅膜的介电常数，能够降低多晶硅绝缘膜的厚度。

公开(公告)号：US06822276B1

公开(公告)日：2004-11-23

申请号：US09391250

申请日：1999-09-07

申请人： Kazuyoshi Torii ,  Hiroshi Miki ,  Yoshihisa Fujisaki

发明人： Kazuyoshi Torii ,  Hiroshi Miki ,  Yoshihisa Fujisaki

IPC分类号： H01L27108

CPC分类号： H01L28/56 ,  H01L21/28568 ,  H01L27/10852 ,  H01L27/10855 ,  H01L28/55 ,  H01L28/75

摘要： It is an object of the present invention to provide a fine memory cell structure preventing a reaction between an interlayer insulating film and a ferroelectric film and suitable for high integration. According to the invention, there is provided a structure in which a reaction barrier film 43 is interposed between a ferroelectric film 71 and an interlayer insulating film 32 and side walls of a diffusion barrier film 51 are not brought into direct contact with the ferroelectric film 71. Thereby, the reaction between the interlayer insulating film 32 and the ferroelectric film 71 can be restrained and exfoliation of the ferroelectric film 71 can be prevented.

摘要翻译： 本发明的目的是提供一种防止层间绝缘膜和铁电体膜之间的反应并且适合于高集成度的精细存储单元结构。 根据本发明，提供一种结构，其中反应阻挡膜43介于铁电膜71和层间绝缘膜32之间，并且扩散阻挡膜51的侧壁不与铁电体膜71直接接触 由此，能够抑制层间绝缘膜32与强电介质膜71的反应，能够防止铁电体膜71的剥离。

公开(公告)号：US06800889B2

公开(公告)日：2004-10-05

申请号：US10073240

申请日：2002-02-13

申请人： Shinichiro Takatani ,  Hiroshi Miki ,  Keiko Kushida ,  Yoshihisa Fujisaki ,  Kazuyoshi Torii

发明人： Shinichiro Takatani ,  Hiroshi Miki ,  Keiko Kushida ,  Yoshihisa Fujisaki ,  Kazuyoshi Torii

IPC分类号： H01L2976

CPC分类号： H01L28/55 ,  H01L28/60

摘要： A semiconductor device includes a capacitor having a lower electrode (102), a high-dielectric-constant or ferroelectric thin film (103), and an upper electrode (104) which are subsequently stacked. An impurity having an action of suppressing the catalytic activity of a metal or a conductive oxide constituting the electrode is added to the upper electrode (104). The addition of the impurity is effective to prevent inconveniences such as a reduction in capacitance, an insulation failure, and the peeling of the electrode due to hydrogen heat-treatment performed after formation of the upper electrode (104), and to improve the long-term reliability.

摘要翻译： 半导体器件包括随后堆叠的具有下电极（102），高介电常数或铁电薄膜（103）和上电极（104）的电容器。 具有抑制构成电极的金属或导电氧化物的催化活性的作用的杂质被添加到上电极（104）。 杂质的添加对于防止在形成上电极（104）之后进行的氢热处理等电容的减少，绝缘失效以及电极的剥离等不良情况是有效的， 长期可靠性。

公开(公告)号：US06509246B2

公开(公告)日：2003-01-21

申请号：US09877207

申请日：2001-06-11

申请人： Hiroshi Miki ,  Yasuhiro Shimamoto ,  Masahiko Hiratani ,  Tomoyuki Hamada

发明人： Hiroshi Miki ,  Yasuhiro Shimamoto ,  Masahiko Hiratani ,  Tomoyuki Hamada

IPC分类号： H01L2120

CPC分类号： H01L28/84 ,  H01L27/10814 ,  H01L28/91

摘要： A semiconductor integrated circuit in which the storage capacitor has an increased capacitance and a decreased leakage current. The storage capacitor is formed by the steps of: forming a polysilicon bottom electrode having semispherical silicon crystals formed thereon; performing plasma nitriding on the surface of said bottom electrode at a temperature lower than 550° C., thereby forming a film of silicon nitride having a film thickness smaller than 1.5 nm; and depositing a film of amorphous tantalum pentoxide and then crystallizing said amorphous tantalum pentoxide. The silicon nitride film has improved resistance to oxidation and also has a reduced leakage current. As a result, the polysilicon bottom electrode becomes resistant to oxidation and the storage capacitor increases in capacitance and decreases in leakage current.

公开(公告)号：US06462368B2

公开(公告)日：2002-10-08

申请号：US10059256

申请日：2002-01-31

申请人： Kazuyoshi Torii ,  Yasuhiro Shimamoto ,  Hiroshi Miki ,  Keiko Kushida ,  Yoshihisa Fujisaki

发明人： Kazuyoshi Torii ,  Yasuhiro Shimamoto ,  Hiroshi Miki ,  Keiko Kushida ,  Yoshihisa Fujisaki

IPC分类号： H01L2976

CPC分类号： H01L27/10855 ,  H01L21/76885 ,  H01L27/10894 ,  H01L28/91

摘要： A diffusion preventive layer extending between the bottom surface of a lower electrode and an interconnection connecting the lower electrode to one of the diffusion layer of a switching transistor is self-aligned. As a result, side trench is produced since a hole pattern is formed by using a dummy film, and even if a contact plug of a memory section is misaligned with the diffusion preventive layer, the contact plug is out of direct contact with a dielectric film having a high permittivity. Hence, a highly reliable device can be obtained.

摘要翻译： 在下电极的底表面和将下电极连接到开关晶体管的扩散层之一的互连之间延伸的扩散防止层是自对准的。 结果，由于通过使用虚拟膜形成孔图案，所以制造侧沟槽，并且即使存储部分的接触插塞与扩散防止层不对准，接触插塞也不与电介质膜直接接触 具有很高的介电常数。 因此，可以获得高度可靠的装置。