公开(公告)号：US06461447B1

公开(公告)日：2002-10-08

申请号：US09607626

申请日：2000-06-30

申请人： Hiroshi Shinyashiki ,  Hiroshi Koya ,  Tomonori Yamaoka ,  Kazuhito Matsukawa ,  Yasuhiro Kimura ,  Hidekazu Yamamoto

发明人： Hiroshi Shinyashiki ,  Hiroshi Koya ,  Tomonori Yamaoka ,  Kazuhito Matsukawa ,  Yasuhiro Kimura ,  Hidekazu Yamamoto

IPC分类号： H01L2900

CPC分类号： C30B29/06 ,  C30B15/203

摘要： A substrate having a surface on which silicon is epitaxially grown; wherein the substrate is cut from an oxygen induced stacking fault generation area of a single crystal silicon rod grown by the Czochralski method.

摘要翻译： 具有外延生长硅的表面的衬底; 其特征在于，所述基板由通过切克劳斯基法（Czochralski）法生长的单晶硅棒的氧诱导堆垛层错产生区切割。

公开(公告)号：US06828163B2

公开(公告)日：2004-12-07

申请号：US10203882

申请日：2002-08-15

申请人： Makoto Kobayashi ,  Kazuhito Matsukawa ,  Hidekazu Yamamoto ,  Shinroku Maejima

发明人： Makoto Kobayashi ,  Kazuhito Matsukawa ,  Hidekazu Yamamoto ,  Shinroku Maejima

IPC分类号： H01L2100

CPC分类号： G01B21/30 ,  H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

摘要： There are provided a method and an apparatus for evaluating a wafer configuration which can accurately evaluate a peripheral portion of a wafer as compared with the conventional SFQR or the like, which comprises: measuring a configuration of a wafer at positions with a prescribed space within a surface of the wafer; providing a first region (W1) within the wafer surface for calculating a reference line or a reference plane from the measured wafer configuration; calculating a reference line (10a) or a reference plane (10b) in the first region (W1); providing a second region (W2) to be evaluated outside the first region; extrapolating the reference line (10a) or reference plane (10b) to the second region (W2); analyzing a difference between the configuration of the second region and the reference line or reference plane within the second region; and calculating the analyzed difference as surface characteristics.

摘要翻译： 提供了一种用于评估晶片配置的方法和装置，该方法和装置可以与传统的SFQR等相比能够精确地评估晶片的周边部分，其包括：在晶片的内部具有规定空间的位置处测量晶片的构造 晶片表面; 在所述晶片表面内提供第一区域（W1），用于从测量的晶片配置计算参考线或参考平面; 在所述第一区域（W1）中计算参考线（10a）或参考平面（10b）; 提供要在第一区域之外评估的第二区域（W2）; 将参考线（10a）或参考平面（10b）外推到第二区域（W2）; 分析第二区域的配置与第二区域内的参考线或参考平面之间的差异; 并计算分析的差异作为表面特征。

公开(公告)号：US20060022321A1

公开(公告)日：2006-02-02

申请号：US11190011

申请日：2005-07-27

申请人： Kazuhito Matsukawa ,  Tsuyoshi Koga ,  Akio Nishida ,  Yoshiko Higashide ,  Jun Shibata ,  Hiroshi Tobimatsu

发明人： Kazuhito Matsukawa ,  Tsuyoshi Koga ,  Akio Nishida ,  Yoshiko Higashide ,  Jun Shibata ,  Hiroshi Tobimatsu

IPC分类号： H01L21/50 ,  H01L23/02

CPC分类号： H01L25/0657 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： In a semiconductor chip A wherein an element layer 2 having transistors and the like is formed on the front face, and the back face is joined to an underlying member, such as a package substrate, the thickness T is made 100 μm or less, and thereafter, a gettering layer 3 is formed on the back face of the semiconductor chip A. The gettering layer 3 is formed, for example, by polishing the back face of said semiconductor chip A using a polishing machine. Thereby, the yield of devices can be improved in the step for assembling the package.

公开(公告)号：US06706636B2

公开(公告)日：2004-03-16

申请号：US10175784

申请日：2002-06-21

申请人： Kazuhito Matsukawa

发明人： Kazuhito Matsukawa

IPC分类号： H01L21302

CPC分类号： H01L21/02032 ,  H01L21/324 ,  Y10S438/906

摘要： A method of regenerating a semiconductor wafer which allows a used wafer, even if the wafer contains a crystal defect such as a COP, to be regenerated into a high-quality semiconductor wafer is provided. A used silicon wafer is polished in a step S1. Next, the used silicon wafer is immersed in mixed acids including at least two kinds of acids in a step S2. A surface treatment is performed on the used silicon wafer to planarize the surface of the used silicon wafer in a step S3. Then, a high temperature annealing process is performed in a step S4, to ultimately obtain a regenerate wafer. The high temperature annealing process includes either a first high temperature annealing process which is performed at a high temperature of 1200° C. or higher in an argon atmosphere for 30 to 60 minutes, or a second high temperature annealing process which is performed at a high temperature of 1200° C. or higher in a hydrogen atmosphere for 30 to 60 minutes.

摘要翻译： 提供了即使将晶片包含诸如COP的晶体缺陷再生成高品质半导体晶片的再生半导体晶片再生方法也可以使用晶片。 在步骤S1中抛光使用的硅晶片。 接下来，在步骤S2中将所使用的硅晶片浸入包含至少两种酸的混合酸中。 在步骤S3中对使用的硅晶片进行表面处理以使所使用的硅晶片的表面平坦化。 然后，在步骤S4中进行高温退火处理，最终获得再生晶片。 高温退火工艺包括在氩气气氛中在1200℃或更高的高温下进行30至60分钟的第一高温退火工艺或在高温下进行的第二高温退火工艺 在氢气氛中温度为1200℃以上30〜60分钟。

公开(公告)号：US5306947A

公开(公告)日：1994-04-26

申请号：US2398

申请日：1993-01-13

申请人： Hiroshi Adachi ,  Hirozoh Kanegae ,  Hiroshi Mochizuki ,  Masanori Obata ,  Takemi Endoh ,  Kimio Hagi ,  Shigeru Harada ,  Kazuhito Matsukawa ,  Akira Ohhisa ,  Etsushi Adachi

发明人： Hiroshi Adachi ,  Hirozoh Kanegae ,  Hiroshi Mochizuki ,  Masanori Obata ,  Takemi Endoh ,  Kimio Hagi ,  Shigeru Harada ,  Kazuhito Matsukawa ,  Akira Ohhisa ,  Etsushi Adachi

IPC分类号： H01L21/3205 ,  H01L21/3105 ,  H01L21/312 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48 ,  H01L29/46 ,  H01L29/54 ,  H01L29/62

CPC分类号： H01L21/02137 ,  H01L21/02282 ,  H01L21/3105 ,  H01L21/31055 ,  H01L21/31058 ,  H01L21/3122 ,  H01L21/76819 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002

摘要： The present invention is mainly characterized by providing an even surface of an interlayer insulating film for insulating and isolating an upper interconnection and a lower interconnection from each other. A lower interconnection layer is provided on a semiconductor substrate, having a pattern of stepped portions. A silicon type insulating film is provided on the semiconductor substrate so as to cover the lower interconnection layer. A silicon ladder resin film is filled in recessed portions of the surface of the silicon type insulating film for making even the surface of the silicon type insulating film. An upper interconnection layer electrically connected to the lower interconnection layer through a via hole is provided on the silicon type insulating film. The silicon ladder resin film has the structural formula: ##STR1## where R.sub.1 is at least one of a phenyl group and a lower alkyl group, R.sub.2 is at least one of a hydrogen atom and a lower alkyl group, and n is an integer of 20 to 1000.

摘要翻译： 本发明的主要特征在于，提供用于使上部互连和下部互连彼此绝缘和隔离的层间绝缘膜的均匀表面。 下部布线层设置在半导体基板上，具有台阶部分的图案。 在半导体衬底上设置硅绝缘膜，以覆盖下互连层。 硅梯型树脂膜填充在硅型绝缘膜的表面的凹部中，以使硅型绝缘膜的表面均匀。 通过通孔电连接到下互连层的上互连层设置在硅型绝缘膜上。 硅梯树脂膜具有结构式：（*化学结构*）其中R 1为苯基和低级烷基中的至少一个，R 2为氢原子和低级烷基中的至少一个，n为 整数为20〜1000。

公开(公告)号：US07582950B2

公开(公告)日：2009-09-01

申请号：US11190011

申请日：2005-07-27

申请人： Kazuhito Matsukawa ,  Tsuyoshi Koga ,  Akio Nishida ,  Yoshiko Higashide ,  Jun Shibata ,  Hiroshi Tobimatsu

发明人： Kazuhito Matsukawa ,  Tsuyoshi Koga ,  Akio Nishida ,  Yoshiko Higashide ,  Jun Shibata ,  Hiroshi Tobimatsu

IPC分类号： H01L29/06

CPC分类号： H01L25/0657 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： In a semiconductor chip A wherein an element layer 2 having transistors and the like is formed on the front face, and the back face is joined to an underlying member, such as a package substrate, the thickness T is made 100 μm or less, and thereafter, a gettering layer 3 is formed on the back face of the semiconductor chip A. The gettering layer 3 is formed, for example, by polishing the back face of said semiconductor chip A using a polishing machine. Thereby, the yield of devices can be improved in the step for assembling the package.

摘要翻译： 在半导体芯片A中，其中在正面上形成具有晶体管等的元件层2，并且背面与诸如封装基板的底层部件接合，厚度T为100μm以下， 此后，在半导体芯片A的背面上形成吸气层3.吸气层3例如通过使用研磨机对所述半导体芯片A的背面进行研磨而形成。 因此，在组装包装的步骤中可以提高装置的产量。

公开(公告)号：US06656775B1

公开(公告)日：2003-12-02

申请号：US09668368

申请日：2000-09-25

申请人： Kazuhito Matsukawa

发明人： Kazuhito Matsukawa

IPC分类号： H01L2100

CPC分类号： H01L29/66742 ,  H01L29/78603

摘要： A semiconductor substrate that suppresses not only auto doping but also warpage can be provided by disposing an oxide film (4) at a position in a semiconductor substrate (1), so as to be apart from a main surface (1a) and a reverse surface (1b). The oxide film (4) can be so disposed that it is apart not less than 200 nm from the reverse surface (1b), and extends throughout the semiconductor substrate (1) in a thickness of 400 to 1000 nm, by implanting oxygen ion from the reverse surface (1b), followed by annealing.

摘要翻译： 可以通过在氧化膜（4）的半导体衬底（1）中的位置处设置氧化膜（4a）与主表面（1a）和反面 （1b）。 氧化膜（4）可以如此设置，使其与反面（1b）分开不小于200nm，并且通过从400nm到1000nm的厚度中的氧离子注入，遍及半导体衬底（1） 反面（1b），然后退火。