公开(公告)号：US07664714B2

公开(公告)日：2010-02-16

申请号：US11255895

申请日：2005-10-21

申请人： Hiroshi Tsujino ,  Nobuaki Miyakawa ,  Gen Matsumoto ,  Ryoji Noyori, legal representative

发明人： Hiroshi Tsujino ,  Nobuaki Miyakawa ,  Gen Matsumoto

IPC分类号： G06N3/02

CPC分类号： G06N3/08 ,  G06N3/049

摘要： A neural network element, outputting an output signal in response to a plurality of input signals, comprises a history memory for accumulating and storing the plurality of input signals in a temporal order as history values. It also includes an output module for outputting the output signal when an internal state exceeds a predetermined threshold value, the internal state being based on a sum of the product of a plurality of input signals and corresponding coupling coefficients. The history values depend on change of the internal state. The neural network element is configured to subtract a predetermined value from the internal state immediately after the output module fires and performs learning for reinforcing or attenuating the coupling coefficient according to the history values after the output module fires.

摘要翻译： 输出响应于多个输入信号的输出信号的神经网络元件包括用于以时间顺序累积并存储多个输入信号作为历史值的历史存储器。 它还包括一个输出模块，用于当内部状态超过预定阈值时输出输出信号，内部状态基于多个输入信号的乘积和相应的耦合系数之和。 历史价值取决于内部状态的变化。 神经网络元件被配置为在输出模块触发之后立即从内部状态减去预定值，并且在输出模块触发之后根据历史值执行用于加强或衰减耦合系数的学习。

公开(公告)号：US20060184465A1

公开(公告)日：2006-08-17

申请号：US11255895

申请日：2005-10-21

申请人： Hiroshi Tsujino ,  Nobuaki Miyakawa ,  Gen Matsumoto

发明人： Hiroshi Tsujino ,  Nobuaki Miyakawa ,  Gen Matsumoto

IPC分类号： G06N3/02

CPC分类号： G06N3/08 ,  G06N3/049

摘要： A neural network element, outputting an output signal in response to a plurality of input signals, comprises a history memory for accumulating and storing the plurality of input signals in a temporal order as history values. It also includes an output module for outputting the output signal when an internal state exceeds a predetermined threshold value, the internal state being based on a sum of the product of a plurality of input signals and corresponding coupling coefficients. The history values depend on change of the internal state. The neural network element is configured to subtract a predetermined value from the internal state immediately after the output module fires and performs learning for reinforcing or attenuating the coupling coefficient according to the history values after the output module fires.

摘要翻译： 输出响应于多个输入信号的输出信号的神经网络元件包括用于以时间顺序累积并存储多个输入信号作为历史值的历史存储器。 它还包括一个输出模块，用于当内部状态超过预定阈值时输出输出信号，内部状态基于多个输入信号的乘积和相应的耦合系数之和。 历史价值取决于内部状态的变化。 神经网络元件被配置为在输出模块触发之后立即从内部状态减去预定值，并且在输出模块触发之后根据历史值执行用于加强或衰减耦合系数的学习。

公开(公告)号：US20100015797A1

公开(公告)日：2010-01-21

申请号：US12063718

申请日：2006-08-25

申请人： Toshio Saito ,  Akira Otaguro ,  Manabu Otake ,  Yoshiya Takahira ,  Namio Katagiri ,  Nobuaki Miyakawa

发明人： Toshio Saito ,  Akira Otaguro ,  Manabu Otake ,  Yoshiya Takahira ,  Namio Katagiri ,  Nobuaki Miyakawa

IPC分类号： H01L21/768

CPC分类号： H01L25/50 ,  H01L21/76898 ,  H01L21/823871 ,  H01L23/481 ,  H01L23/585 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L27/0694 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

摘要： When a tungsten film (43) is embedded inside of a conductive groove (4A) formed in a wafer (W2) and a silicon oxide film (36) thereon and having a high aspect ratio, film formation and etch back of the tungsten film (43) are successively performed in a chamber of the same apparatus, therefore, a film thickness of the tungsten film (43) deposited in one film formation step is made to be thin. Whereby problems, such as exfoliation of the tungsten film (43), generation of micro-cracks, and occurrence of warpage and cracks of the wafer (W2), are avoided.

摘要翻译： 当将钨膜（43）嵌入形成在晶片（W2）和氧化硅膜（36）上的导电槽（4A）内并具有高纵横比，钨膜的成膜和回蚀（ 43）在相同装置的腔室中连续地进行，因此，在一个成膜步骤中沉积的钨膜（43）的膜厚变薄。 由此，避免了钨膜（43）的剥离，微裂纹的产生，以及晶片（W2）的翘曲和裂纹的发生等问题。

公开(公告)号：US6026422A

公开(公告)日：2000-02-15

申请号：US31889

申请日：1998-02-27

申请人： So Yamada ,  Shinjiro Inabata ,  Nobuaki Miyakawa

发明人： So Yamada ,  Shinjiro Inabata ,  Nobuaki Miyakawa

IPC分类号： G06F17/12 ,  G06F17/10 ,  G06F17/11

CPC分类号： G06F17/10

摘要： Electron repulsion integrals are classified according to atomic nucleus coordinates, etc., coefficients are generated and are stored in a data memory, multiplication with addition operation is executed according to a product sum procedure of auxiliary integrals of recursive order 1 or less, and the result is stored in the data memory. Next, density matrix element is stored in the data memory, a multiplication with addition operation procedure of an electron repulsion integral of recursive order 2 not containing any procedure of recursive order 1 or less is generated, and an instruction memory is updated. Multiplication with addition operation is executed while data is read from the data memory, and the result is stored in the data memory. At the termination of the product sum procedure, calculation of electron repulsion integral gRstu is complete and the Fock matrix element value is updated. The Fock matrix element containing electron repulsion integral when a linear combination constant to minimize the expected value of molecule energy required for molecular orbital calculation is found is thus found by performing recursive multiplication with addition operation.

摘要翻译： 电子排斥积分根据原子核坐标等进行分类，生成系数并存储在数据存储器中，根据递归顺序1或更小的辅助积分的乘积和过程执行与加法运算相乘的乘法运算，结果 存储在数据存储器中。 接下来，密度矩阵元素被存储在数据存储器中，产生与不包含递归顺序1或更小的任何过程的递归阶数2的电子排斥积分的加法运算过程相乘，并且更新指令存储器。 在从数据存储器读取数据的同时执行加法运算的乘法运算，结果存储在数据存储器中。 在产品和程序结束时，电子排斥积分gRstu的计算完成，更新了Fock矩阵元素值。 因此，通过执行加法运算的递归乘法，可以发现，当发现分子轨道计算所需分子能量的期望值最小化的线性组合常数时，含有电子斥力积分的Fock矩阵元素。

公开(公告)号：US5596511A

公开(公告)日：1997-01-21

申请号：US186029

申请日：1994-01-25

申请人： Shinjiro Toyoda ,  Hitoshi Ikeda ,  Eiri Hashimoto ,  Nobuaki Miyakawa

发明人： Shinjiro Toyoda ,  Hitoshi Ikeda ,  Eiri Hashimoto ,  Nobuaki Miyakawa

IPC分类号： G06F17/50 ,  G06F17/00

CPC分类号： G06F19/701

摘要： A proximal particle list including numbers of particles located within a predetermined distance from a particular particle is generated in calculating a Coulomb force acting on a particular particle or a related potential. A van der Waals force acting on the particular particle or a related potential is thereafter calculated based on only the particles included in the proximal particle list.

摘要翻译： 在计算作用于特定颗粒或相关电位的库仑力时，产生包括位于特定颗粒的预定距离内的颗粒数的近端粒子列表。 此后，仅基于近端粒子列表中包含的粒子计算作用于特定粒子或相关电位的范德华力。

公开(公告)号：US4665505A

公开(公告)日：1987-05-12

申请号：US685552

申请日：1984-12-24

申请人： Nobuaki Miyakawa ,  Yoshiaki Yazawa ,  Shoichi Ozeki ,  Kinya Mitsumoto

发明人： Nobuaki Miyakawa ,  Yoshiaki Yazawa ,  Shoichi Ozeki ,  Kinya Mitsumoto

IPC分类号： G11C11/413 ,  G11C7/10 ,  G11C11/40

CPC分类号： G11C7/1096 ,  G11C7/1078

摘要： A write circuit for a semiconductor storage device which comprises a data output stage constructed by a composite circuit including at least one MOS transistor logic circuit and bipolar transistor. The Mos transistor circuit operates in response to an input signal to control the on-off states of at least one of the bipolar transistors. The write circuit implements less power consumption.

摘要翻译： 一种用于半导体存储装置的写入电路，包括由包括至少一个MOS晶体管逻辑电路和双极晶体管的复合电路构成的数据输出级。 Mos晶体管电路响应于输入信号而工作，以控制至少一个双极晶体管的导通截止状态。 写入电路实现更少的功耗。

公开(公告)号：US20100164055A1

公开(公告)日：2010-07-01

申请号：US12718061

申请日：2010-03-05

申请人： Nobuaki Miyakawa ,  Takanori Maebashi ,  Takahiro Kimura

发明人： Nobuaki Miyakawa ,  Takanori Maebashi ,  Takahiro Kimura

IPC分类号： H01L23/48

CPC分类号： H01L25/117 ,  H01L21/6835 ,  H01L21/76898 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/81139 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2924/01019 ,  H01L2924/01037 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

摘要： A deep isolation trench extending from the main surface of a substrate to a desired depth is formed on the substrate with an insulating film in buried in it to form a through isolation portion. Subsequently, after a MOSFET is formed on the main surface of the substrate, an interlayer insulating film is deposited on the main surface of the substrate. Then, a deep conduction trench extending from the upper surface of the interlayer insulating film to a depth within the thickness of the substrate is formed in a region surrounded by the through isolation potion. Subsequently, a conductive film is buried in the deep conduction trench to form through interconnect portion. Then, after the undersurface of the substrate is ground and polished to an extent not to expose the through isolation portion and the through interconnect portion, wet etching is performed to an extent to expose parts of the lower portion of each of the through isolation portion and the through interconnect portion.

摘要翻译： 在衬底上形成有从衬底的主表面延伸到所需深度的深度隔离沟槽，其中埋置有绝缘膜以形成通过隔离部分。 随后，在衬底的主表面上形成MOSFET之后，在衬底的主表面上沉积层间绝缘膜。 然后，在由直通隔离部包围的区域中形成从层间绝缘膜的上表面延伸到衬底厚度内的深度的深导电沟槽。 随后，将导电膜埋入深导电沟槽中以形成通过互连部分。 然后，在将基板的下表面研磨抛光至不暴露通过隔离部分和通过互连部分的程度之后，进行湿法蚀刻，使其暴露于每个通过隔离部分的下部的部分，以及 直通互连部分。

公开(公告)号：US07705455B2

公开(公告)日：2010-04-27

申请号：US12064762

申请日：2006-08-25

申请人： Nobuaki Miyakawa ,  Takanori Maebashi ,  Takahiro Kimura

发明人： Nobuaki Miyakawa ,  Takanori Maebashi ,  Takahiro Kimura

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L25/117 ,  H01L21/6835 ,  H01L21/76898 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/81139 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2924/01019 ,  H01L2924/01037 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

摘要： A deep isolation trench extending from the main surface of a substrate to a desired depth is formed on the substrate with an insulating film in buried in it to form a through isolation portion. Subsequently, after a MOSFET is formed on the main surface of the substrate, an interlayer insulating film is deposited on the main surface of the substrate. Then, a deep conduction trench extending from the upper surface of the interlayer insulating film to a depth within the thickness of the substrate is formed in a region surrounded by the through isolation portion. Subsequently, a conductive film is buried in the deep conduction trench to form through interconnect portion. Then, after the undersurface of the substrate is ground and polished to an extent not to expose the through isolation portion and the through interconnect portion, wet etching is performed to an extent to expose parts of the lower portion of each of the through isolation portion and the through interconnect portion.

摘要翻译： 在衬底上形成有从衬底的主表面延伸到所需深度的深度隔离沟槽，其中埋置有绝缘膜以形成通过隔离部分。 随后，在衬底的主表面上形成MOSFET之后，在衬底的主表面上沉积层间绝缘膜。 然后，在由通过隔离部包围的区域中形成从层间绝缘膜的上表面延伸到衬底厚度内的深度的深导电沟槽。 随后，将导电膜埋在深导电沟槽中以形成通过互连部分。 然后，在将基板的下表面研磨抛光至不暴露通过隔离部分和通过互连部分的程度之后，进行湿法蚀刻，使其暴露于每个通过隔离部分的下部的部分，以及 直通互连部分。

公开(公告)号：US20090206469A1

公开(公告)日：2009-08-20

申请号：US12369456

申请日：2009-02-11

申请人： Takanori MAEBASHI ,  Nobuaki Miyakawa

发明人： Takanori MAEBASHI ,  Nobuaki Miyakawa

IPC分类号： H01L23/538 ,  H01L21/98

CPC分类号： H01L23/481 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/05001 ,  H01L2224/11 ,  H01L2224/13 ,  H01L2224/13009 ,  H01L2224/13022 ,  H01L2224/16 ,  H01L2224/16146 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/00

摘要： A semiconductor device has a plurality of wafers which are laminated to each other, wherein: each wafer includes an lamination surface to which another wafer is laminated and a substrate having an element formed thereon; the lamination surface is provided with an electric signal connecting portion that electrically connects to said another wafer so as to form a semiconductor circuit; at least one of the electrical signal connecting portions facing each other is a protruding connection portion that protrudes from a region which exposes the substrate on the lamination surface; and a reinforcing protruding portion that is insulated from the semiconductor circuit, and is formed of the same material as the substrate to protrude from the lamination surface with a height equal to the length of a gap between the lamination surfaces of wafers facing each other is provided in an area where the protruding connection portion is not disposed on the lamination surface formed with the protruding connection portion.

摘要翻译： 半导体器件具有彼此层叠的多个晶片，其中：每个晶片包括层叠另一晶片的层叠表面和形成有元件的衬底; 层叠表面设置有电连接到所述另一晶片的电信号连接部分，以形成半导体电路; 电信号连接部中的至少一个彼此面对的是突出的连接部，其从层叠面上露出基板的区域突出; 和与半导体电路绝缘的加强突出部分，并且由与层叠表面突出的相同材料形成，其高度等于彼此面对的晶片的层叠表面之间的间隙的长度 在突起连接部未设置在形成有突出连接部的层叠面上的区域中。

公开(公告)号：US20090174080A1

公开(公告)日：2009-07-09

申请号：US12063606

申请日：2006-08-25

申请人： Toshio Saito ,  Satoshi Moriya ,  Morio Nakamura ,  Goichi Yokoyama ,  Tatsuyuki Saito ,  Nobuaki Miyakawa

发明人： Toshio Saito ,  Satoshi Moriya ,  Morio Nakamura ,  Goichi Yokoyama ,  Tatsuyuki Saito ,  Nobuaki Miyakawa

IPC分类号： H01L23/522

CPC分类号： H01L25/0657 ,  H01L21/763 ,  H01L21/76898 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/45 ,  H01L24/48 ,  H01L25/50 ,  H01L27/0203 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

摘要： In order to improve the manufacturing yield of a semiconductor device having a three-dimensional structure in which a plurality of chips are stacked and attached to each other, the opening shape of each of conductive grooves (4A) formed in each chip (C2) obtained from a wafer (W2) is rectangular, and the number of the conductive grooves (4A) whose long-sides are directed in a Y direction and the number of the conductive grooves (4A) whose long-sides are directed in an X direction perpendicular to the Y direction are made to be approximately equal to each other number in the entire wafer (W2), whereby the film stress upon embedding of a conductive film into the interior of the conductive grooves is reduced, and generation of exfoliation and micro-cracks in the conductive film or warpage and cracks of the wafer (W2) are prevented.

摘要翻译： 为了提高具有多个芯片彼此堆叠并附接的三维结构的半导体器件的制造成品，形成在每个芯片（C2）中的每个导电槽（4A）的开口形状获得 从晶片（W2）的长方形的长方形的导体槽（4A）的长度方向的长度方向的数量和长边方向的X方向的导体槽的数量 使整个晶片（W2）的Y方向大致相等，由此导电膜嵌入导电槽内的膜应力减小，剥离和微裂纹的产生 导致膜或翘曲和晶片（W2）的裂纹被阻止。