公开(公告)号：US5643805A

公开(公告)日：1997-07-01

申请号：US401678

申请日：1995-03-10

申请人： Hiroyuki Ohta ,  Hideo Miura ,  Hiroo Masuda ,  Yoichi Tamaki ,  Takahide Ikeda ,  Asao Nishimura ,  Takashi Hashimoto

发明人： Hiroyuki Ohta ,  Hideo Miura ,  Hiroo Masuda ,  Yoichi Tamaki ,  Takahide Ikeda ,  Asao Nishimura ,  Takashi Hashimoto

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L23/485 ,  H01L27/06 ,  H01L29/732 ,  H01L21/265

CPC分类号： H01L23/4855 ,  H01L23/485 ,  H01L2924/0002 ,  Y10S148/01 ,  Y10S148/124 ,  Y10S148/135

摘要： A bipolar device having a level difference between the contact area level of a base electrode and a base region in a silicon substrate, and the contact area level of an emitter electrode and an emitter region in the silicon substrate in the range of 0.03 .mu.m to 0.1 .mu.m by removing undesirable impurities from the emitter region and a predetermined horizontal distance between a sidewall and a device isolation film does not generate dislocation and show good electric characteristics.

摘要翻译： 具有硅基板中的基极的接触面积电平与基极区域之间的电平差的硅双极器件，以及硅基板的发射电极和发射极区域的接触面积电平为0.03μm〜 通过从发射极区域去除不需要的杂质并且侧壁和器件隔离膜之间的预定水平距离不产生位错并且显示出良好的电特性，0.1μm。

公开(公告)号：US5619069A

公开(公告)日：1997-04-08

申请号：US458655

申请日：1995-06-02

申请人： Hiroyuki Ohta ,  Hideo Miura ,  Hiroo Masuda ,  Yoichi Tamaki ,  Takahide Ikeda ,  Asao Nishimura ,  Takashi Hashimoto

发明人： Hiroyuki Ohta ,  Hideo Miura ,  Hiroo Masuda ,  Yoichi Tamaki ,  Takahide Ikeda ,  Asao Nishimura ,  Takashi Hashimoto

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L23/485 ,  H01L27/06 ,  H01L29/732 ,  H01L23/48

CPC分类号： H01L23/4855 ,  H01L23/485 ,  H01L2924/0002 ,  Y10S148/01 ,  Y10S148/124 ,  Y10S148/135

摘要： A bipolar device having a level difference between the contact area level of a base electrode and a base region in a silicon substrate, and the contact area level of an emitter electrode and an emitter region in the silicon substrate in the range of 0.03 .mu.m to 0.1 .mu.m by removing undesirable impurities from the emitter region and a predetermined horizontal distance between a sidewall and a device isolation film does not generate dislocation and show good electric characteristics.

摘要翻译： 具有硅基板中的基极的接触面积电平与基极区域之间的电平差的硅双极器件，以及硅基板的发射电极和发射极区域的接触面积电平为0.03μm〜 通过从发射极区域去除不需要的杂质并且侧壁和器件隔离膜之间的预定水平距离不产生位错并且显示出良好的电特性，0.1μm。

公开(公告)号：US06337517B1

公开(公告)日：2002-01-08

申请号：US09151590

申请日：1998-09-11

申请人： Hiroyuki Ohta ,  Hideo Miura ,  Kazushige Sato ,  Takeshi Kimura ,  Hiroo Masuda

发明人： Hiroyuki Ohta ,  Hideo Miura ,  Kazushige Sato ,  Takeshi Kimura ,  Hiroo Masuda

IPC分类号： H01L2348

CPC分类号： H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device capable of operating at a high speed or of having many functions. In this device, delamination of buried electrodes is prevented and thus high reliability is offered. The depth A of contact holes, the minimum linewidth R of a lower metallization layer, and the thickness B of the lower metallization layer satisfy relations given by (0.605/R)0.5

摘要翻译： 能够高速运转或具有许多功能的半导体装置。 在该装置中，防止了埋入电极的分层，从而提供了高可靠性。 接触孔的深度A，下部金属化层的最小线宽R和下部金属化层的厚度B满足关系式

公开(公告)号：US06326284B1

公开(公告)日：2001-12-04

申请号：US08610488

申请日：1996-03-04

申请人： Hideo Miura ,  Shuji Ikeda ,  Norio Suzuki ,  Yasuhide Hagiwara ,  Hiroyuki Ohta ,  Asao Nishimura

发明人： Hideo Miura ,  Shuji Ikeda ,  Norio Suzuki ,  Yasuhide Hagiwara ,  Hiroyuki Ohta ,  Asao Nishimura

IPC分类号： H01L2176

CPC分类号： H01L21/28185 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/321 ,  H01L21/76202 ,  H01L29/518

摘要： A semiconductor device produced by forming an oxide film on a substrate, heat treating the oxide film at a temperature of 800° C. or higher in an inert atmosphere, followed by conventional steps for formation of a transistor, is improved in electrical reliability due to relaxation of stress generated in the oxide film or in the surface of substrate.

摘要翻译： 通过在基板上形成氧化膜而制造的半导体装置，在惰性气氛中，在800℃以上的温度下进行氧化膜的热处理，接着是用于形成晶体管的常规步骤，由于 松弛在氧化膜或衬底表面产生的应力。

公开(公告)号：US06960832B2

公开(公告)日：2005-11-01

申请号：US10761333

申请日：2004-01-22

申请人： Hiromi Shimazu ,  Tomio Iwasaki ,  Hiroyuki Ohta ,  Hideo Miura ,  Shuji Ikeda

发明人： Hiromi Shimazu ,  Tomio Iwasaki ,  Hiroyuki Ohta ,  Hideo Miura ,  Shuji Ikeda

IPC分类号： H01L21/285 ,  H01L21/336 ,  H01L21/768 ,  H01L23/12 ,  H01L21/00

CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L21/76877

摘要： In a semiconductor device having a cobalt silicide film, at least nickel or iron is contained in the cobalt silicide film for preventing the rise of resistance incidental to thinning of the film.

摘要翻译： 在具有钴硅化物膜的半导体器件中，钴硅化物膜中至少含有镍或铁，以防止附着于薄膜变薄的电阻上升。

公开(公告)号：US06856021B1

公开(公告)日：2005-02-15

申请号：US09648455

申请日：2000-08-28

申请人： Tomio Iwasaki ,  Hideo Miura ,  Takashi Nakajima ,  Hiroyuki Ohta ,  Shinji Nishihara ,  Masashi Sahara

发明人： Tomio Iwasaki ,  Hideo Miura ,  Takashi Nakajima ,  Hiroyuki Ohta ,  Shinji Nishihara ,  Masashi Sahara

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532

CPC分类号： H01L21/76844 ,  H01L21/32051 ,  H01L21/76843 ,  H01L21/7685 ,  H01L23/53219 ,  H01L23/53223 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is provided which includes a semiconductor substrate, metal conductors formed on a side of a main face of the substrate, which metal conductors contain aluminum as a main constituent thereof, and copper as an additive element, the metal conductors being made to contain such an element as to suppress the precipitation of copper or being made to have such a film adjacent to the metal conductor as to suppress the precipitation of copper or being made to have such a film adjacent to the metal conductor as to suppress the precipitation of copper.

摘要翻译： 提供了一种半导体器件，其包括半导体衬底，形成在衬底的主面一侧的金属导体，该金属导体以铝为主要成分，铜作为添加元素，金属导体被制成含有 抑制铜的析出或使金属导体附近具有这样的膜的元素，以抑制铜的沉淀，或者使该膜与金属导体相邻，以抑制铜的析出 。

公开(公告)号：US06566149B1

公开(公告)日：2003-05-20

申请号：US09787250

申请日：2001-03-16

申请人： Masatoshi Kanamaru ,  Atsushi Hosogane ,  Yoshihige Endou ,  Ryuji Kouno ,  Hideo Miura ,  Shinji Tanaka ,  Hiroyuki Ohta ,  Akihiko Ariga ,  Naoto Ban ,  Hideyuki Aoki

发明人： Masatoshi Kanamaru ,  Atsushi Hosogane ,  Yoshihige Endou ,  Ryuji Kouno ,  Hideo Miura ,  Shinji Tanaka ,  Hiroyuki Ohta ,  Akihiko Ariga ,  Naoto Ban ,  Hideyuki Aoki

IPC分类号： G01R3126

CPC分类号： G01R3/00

摘要： For an inspection tray, a silicon substrate including a beam or a diaphragm, a probe and wiring is used. To highly accurately position a chip to be inspected, a second substrate for alignment is disposed on the substrate. To position the probe having wiring disposed on the first substrate and the electrode pad of the chip to be inspected, a projection or a groove is formed in each of both substrates. Preferably, the projection or groove should be formed by silicon anisotorpic etching to have a (111) crystal surface. As another machining method, dry etching can be used for machining the positioning projection or groove. By using an inductively coupled plasma-reactive ion etching (ICP-RIE) device for the dry etching, a vertical column or groove can be easily machined.

摘要翻译： 对于检查托盘，使用包括梁或隔膜，探针和布线的硅基板。 为了高精度地定位待检查的芯片，在基板上设置用于对准的第二基板。 为了定位具有设置在第一基板上的布线的探针和要检查的芯片的电极焊盘，在两个基板中的每一个中形成突起或凹槽。 优选地，突起或凹槽应由硅各向异性蚀刻形成以具有（111）晶体表面。 作为另一种加工方法，可以使用干蚀刻来加工定位突起或凹槽。 通过使用用于干蚀刻的电感耦合等离子体反应离子蚀刻（ICP-RIE）装置，可以容易地加工垂直的柱或槽。

公开(公告)号：US06544884B2

公开(公告)日：2003-04-08

申请号：US10022525

申请日：2001-12-20

申请人： Hiroyuki Ohta ,  Hideo Miura ,  Kazushige Sato ,  Takeshi Kimura ,  Hiyoo Masuda

发明人： Hiroyuki Ohta ,  Hideo Miura ,  Kazushige Sato ,  Takeshi Kimura ,  Hiyoo Masuda

IPC分类号： H01L214763

CPC分类号： H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device capable of operating at a high speed or of having many functions. In this device, delamination of buried electrodes is prevented and thus high reliability is offered. The depth A of contact holes, the minimum linewidth R of a lower metallization layer, and the thickness B of the lower metallization layer satisfy relations given by (0.605/R)0.5

公开(公告)号：US06468845B1

公开(公告)日：2002-10-22

申请号：US09536642

申请日：2000-03-28

申请人： Takashi Nakajima ,  Hideo Miura ,  Hiroyuki Ohta ,  Noriaki Okamoto

发明人： Takashi Nakajima ,  Hideo Miura ,  Hiroyuki Ohta ,  Noriaki Okamoto

IPC分类号： H01L2184

CPC分类号： H01L21/28097 ,  H01L21/28035 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/32053 ,  H01L21/76838 ,  H01L21/76877 ,  H01L21/823437 ,  H01L23/485 ,  H01L23/53257 ,  H01L23/53271 ,  H01L28/40 ,  H01L29/4925 ,  H01L29/4975 ,  H01L2924/0002 ,  Y10T117/10 ,  Y10T117/1004 ,  H01L2924/00

摘要： In forming an electrode 2 on a silicon oxide film 5 on a semiconductor substrate 4 through a silicon oxide film 5, for example, the gate electrode 2 is structured in a laminated structure of a plurality of polycrystalline silicon layers 6. The portion of the gate electrode 2 is formed by a method of manufacturing a thin film having a process of depositing amorphous layers and a process of crystallizing (recrystallizing) this amorphous material. In this case, depositing of the amorphous layers is carried out dividedly by a plurality of times so that the thickness of an amorphous layer to be deposited at one time is not larger than a thickness to be prescribed by a critical stress value determined according to a fail event, the amorphous material is crystallized after each process of depositing each amorphous layer has been finished, and the process of depositing amorphous layers and the process of crystallizing the amorphous material are repeated, whereby a laminated structure of the polycrystalline layer 6 having a necessary film thickness is obtained. With the above-described arrangement, it is possible to prevent a deterioration of electric characteristics of a semiconductor device and an occurrence of a defect, such as a peeling off between layers, cracks in a layer, etc., and it is possible to obtain a polycrystalline layer of small grain size in a desired film thickness by a lamination of polycrystalline materials.

摘要翻译： 例如，通过氧化硅膜5在半导体衬底4上的氧化硅膜5上形成电极2时，栅电极2被构成为多个多晶硅层6的层叠结构。栅极部分 通过制造具有沉积非晶层的工艺的薄膜的方法和使该非晶材料结晶（再结晶）的方法形成电极2。 在这种情况下，非晶层的沉积被分开多次进行，使得一次沉积的非晶层的厚度不大于根据根据下式确定的临界应力值规定的厚度 在每个非晶层的沉积过程完成之后，非晶材料结晶，重复沉积非晶层的过程和结晶非晶材料的过程，由此多晶层6的层压结构具有必要的 获得膜厚度。 利用上述结构，可以防止半导体器件的电特性的恶化和层之间的剥离等缺陷的发生，层中的裂纹等，并且可以获得 通过多晶材料的层叠，具有所需膜厚度的小晶粒尺寸的多晶层。

公开(公告)号：US07244643B2

公开(公告)日：2007-07-17

申请号：US10496766

申请日：2002-11-21

申请人： Norio Ishitsuka ,  Yukihiro Kumagai ,  Hideo Miura ,  Shuji Ikeda ,  Toshifumi Takeda ,  Hiroyuki Ohta

发明人： Norio Ishitsuka ,  Yukihiro Kumagai ,  Hideo Miura ,  Shuji Ikeda ,  Toshifumi Takeda ,  Hiroyuki Ohta

IPC分类号： H01L21/8238

CPC分类号： H01L29/7846 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/7842

摘要： The object of the present invention is to provide a semiconductor device comprising an n-type channel field effect transistor and a p-type channel field effect transistor, which has a high degree of reliability and excellent drain current characteristics. The gist of the invention for attaining the object resides in disposing a silicon nitride film to the side wall of a trench for an active region in which the n-type channel field effect transistor is formed and disposing the silicon nitride film only in the direction perpendicular to the channel direction to the sidewall of the trench for the active region of the p-type channel field effect transistor. According to the present invention, a semiconductor device comprising an n-type channel field effect transistor and a p-type channel field effect transistor of excellent current characteristics can be provided.

摘要翻译： 本发明的目的是提供一种包括n型沟道场效应晶体管和p型沟道场效应晶体管的半导体器件，其具有高可靠性和优异的漏极电流特性。 实现本发明的要点在于，在形成有n型沟道场效应晶体管的有源区的沟槽的侧壁上设置氮化硅膜，仅在垂直方向上设置氮化硅膜 到通道方向，到p型沟道场效应晶体管的有源区的沟槽的侧壁。 根据本发明，可以提供包括n型沟道场效应晶体管和具有优异电流特性的p型沟道场效应晶体管的半导体器件。