公开(公告)号：US5585676A

公开(公告)日：1996-12-17

申请号：US228654

申请日：1994-04-18

申请人： Hisanori Uda ,  Tetsuro Sawai ,  Toshikazu Imaoka ,  Toshikazu Hirai ,  Yasoo Harada

发明人： Hisanori Uda ,  Tetsuro Sawai ,  Toshikazu Imaoka ,  Toshikazu Hirai ,  Yasoo Harada

IPC分类号： H01L21/60 ,  H01L23/485 ,  H01L23/50 ,  H01L27/02 ,  H01L27/06 ,  H01L23/48

CPC分类号： H01L24/06 ,  H01L23/50 ,  H01L24/49 ,  H01L27/0207 ,  H01L2224/05599 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/48257 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L24/48 ,  H01L27/0605 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/1306 ,  H01L2924/13063 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/19041 ,  H01L2924/19107

摘要： An IC chip characterized in that at least two input pads and at least two output pads are respectively disposed symmetrical to each other about the center of the IC chip, at least two input/output pads are disposed symmetrical to each other about the center, at least one supply voltage pad is disposed in each of four equal sections formed by longitudinally and laterally dividing the IC chip, and at least one control voltage pad is disposed in each of these four sections. The IC chip can be connected by bonding to various types of IC packages having different configurations of the pins only by mounting in a proper direction without causing the bonding wires to bridge over the other constituent elements or to cross each other.

摘要翻译： 一种IC芯片，其特征在于，至少两个输入焊盘和至少两个输出焊盘分别围绕IC芯片的中心彼此对称地布置，至少两个输入/输出焊盘相对于中心彼此对称地设置， 在通过纵向和横向分割IC芯片形成的四个相等部分中的每一个中设置至少一个电源电压焊盘，并且在这四个部分中的每一个中设置至少一个控制电压焊盘。 IC芯片可以通过仅通过以适当的方向安装而不会使接合线桥接在其他构成元件上或彼此交叉的方式通过结合到具有不同构造的引脚的各种类型的IC封装来连接。

公开(公告)号：US5559457A

公开(公告)日：1996-09-24

申请号：US215193

申请日：1994-03-21

申请人： Hisanori Uda ,  Tetsuro Sawai ,  Toshikazu Imaoka ,  Toshikazu Hirai ,  Yasoo Harada

发明人： Hisanori Uda ,  Tetsuro Sawai ,  Toshikazu Imaoka ,  Toshikazu Hirai ,  Yasoo Harada

IPC分类号： H03D7/00 ,  H03D7/12 ,  H03D7/14 ,  H03D9/06 ,  H04B1/28 ,  H04B1/26

CPC分类号： H03D7/1441 ,  H03D7/1458 ,  H03D2200/0007 ,  H03D2200/0084 ,  H03D2200/0088 ,  H03D7/125 ,  H03D9/0658

摘要： A double-balanced mixer circuit which consumes less power, and is capable of operating on a low voltage power source, because an output of a first signal having a phase lag of 90.degree. from a first frequency signal and an output of a second signal having a phase lead of 90.degree. over the first frequency signal are provided by means of a first phase shifter, an output of a third signal having a phase lag of 90.degree. from a second frequency signal and an output of fourth signal having a phase lead of 90.degree. over the second frequency signal are provided by means of a second phase shifter, thereby generating a radio frequency signal by mixing the first signal and the third signal in a first dual gate circuit, and generating a radio frequency signal by mixing the second signal and the fourth signal in a second dual gate circuit.

摘要翻译： 一种双平衡混频器电路，其消耗较少的功率，并且能够在低电压电源上工作，因为与第一频率信号相差90度的第一信号的输出和具有第一信号的第二信号的输出， 通过第一移相器提供90°以上的第一频率信号的相位引导，从第二频率信号输出具有90°的相位滞后的第三信号和具有相位引导的第四信号的输出 通过第二移相器提供第二频率信号的90°，从而通过在第一双门电路中混合第一信号和第三信号来产生射频信号，并且通过混合第二信号来产生射频信号 以及第二双门电路中的第四信号。

公开(公告)号：US5590412A

公开(公告)日：1996-12-31

申请号：US342220

申请日：1994-11-18

申请人： Tetsuro Sawai ,  Hisanori Uda ,  Toshikazu Hirai ,  Toshikazu Imaoka ,  Yasoo Harada ,  Keiichi Honda ,  Masao Nishida

发明人： Tetsuro Sawai ,  Hisanori Uda ,  Toshikazu Hirai ,  Toshikazu Imaoka ,  Yasoo Harada ,  Keiichi Honda ,  Masao Nishida

IPC分类号： H03F3/193 ,  H03F3/72 ,  H04B1/44 ,  H04B1/48 ,  H03F3/62

CPC分类号： H04B1/44 ,  H03F3/1935 ,  H03F3/72 ,  H04B1/48

摘要： A communication apparatus for use in a portable telephone is disclosed which has a transmit-receive common amplifier for amplifying a transmitted signal or received signal, and a mixer for frequency-mixing the transmitted signal or the received signal with a local oscillator output, wherein connection between the mixer and an input side of the amplifier and connection between the mixer and an output side of the amplifier are made by means of respective signal-path selector switches. During reception, a deep bias is applied to an FET of the transmit-receive common amplifier to reduce current consumption, and during transmission, a shallow bias is applied to the FET of the transmit-receive common amplifier for increased output.

摘要翻译： 公开了一种用于便携式电话的通信装置，其具有用于放大发射信号或接收信号的发射 - 接收公共放大器，以及用本地振荡器输出对发射信号或接收信号进行频率混频的混频器，其中连接 在混频器和放大器的输入侧之间，混频器和放大器的输出侧之间的连接通过相应的信号路径选择器开关进行。 在接收期间，向发射接收公共放大器的FET施加深偏压以减少电流消耗，并且在传输期间，将浅偏压施加到发射 - 接收公共放大器的FET以增加输出。

公开(公告)号：US07206552B2

公开(公告)日：2007-04-17

申请号：US10105802

申请日：2002-03-26

申请人： Tetsuro Asano ,  Toshikazu Hirai

发明人： Tetsuro Asano ,  Toshikazu Hirai

IPC分类号： H04B1/44 ,  H01L29/06 ,  H01L31/00

CPC分类号： H01L29/812 ,  H01L27/0605

摘要： A semiconductor switching device includes two FETs with different device characteristics, a common input terminal, and two output terminals. The gate width of each FET is about 400 μm, and the maximum power required for the device operation is maintained by a lager conductivity of the channel layer of one FET and by a lower conductivity of the channel layer of another FET. The device operates at frequencies of 2.4 GHz or higher without use of shunt FET.

摘要翻译： 半导体开关器件包括具有不同器件特性的两个FET，公共输入端子和两个输出端子。 每个FET的栅极宽度约为400μm，器件操作所需的最大功率由一个FET的沟道层的较大电导率和另一个FET的沟道层的较低电导率保持。 该器件在2.4 GHz或更高的频率下工作，无需使用分流FET。

公开(公告)号：US06903426B2

公开(公告)日：2005-06-07

申请号：US10153857

申请日：2002-05-24

申请人： Tetsuro Asano ,  Toshikazu Hirai ,  Mikito Sakakibara

发明人： Tetsuro Asano ,  Toshikazu Hirai ,  Mikito Sakakibara

IPC分类号： H01L21/822 ,  H01L21/8232 ,  H01L27/04 ,  H01L27/06 ,  H01L27/095 ,  H03K17/00 ,  H01L29/76

CPC分类号： H01L27/0605

摘要： A semiconductor switching device includes two FETs with different device characteristics, a common input terminal, and two output terminals. A signal transmitting FET has a gate width of 500 μm and a signal receiving FET has a gate width of 400 μm. A resistor connecting a gate electrode and a control terminal of the signal transmitting FET is tightly configured to provide expanding space for the FET. Despite the reduced size, the switching device can allow a maximum power of 22.5 dBm to pass through because of the asymmetrical device design. The switching device operates at frequencies of 2.4 GHz or higher without use of shunt FET.

摘要翻译： 半导体开关器件包括具有不同器件特性的两个FET，公共输入端子和两个输出端子。 信号发送FET的栅极宽度为500μm，信号接收FET的栅极宽度为400μm。 连接信号传输FET的栅电极和控制端的电阻被紧密地配置成为FET提供扩展空间。 尽管尺寸减小，但由于不对称的器件设计，开关器件可以允许22.5dBm的最大功率通过。 开关器件在2.4GHz或更高的频率下工作，不使用分流FET。

公开(公告)号：US08742506B2

公开(公告)日：2014-06-03

申请号：US13475375

申请日：2012-05-18

申请人： Tetsuro Asano ,  Mikito Sakakibara ,  Toshikazu Hirai

发明人： Tetsuro Asano ,  Mikito Sakakibara ,  Toshikazu Hirai

IPC分类号： H01L29/861

CPC分类号： H01L27/0255 ,  H01L24/48 ,  H01L27/0248 ,  H01L27/0288 ,  H01L29/66098 ,  H01L29/80 ,  H01L29/812 ,  H01L29/861 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/85399 ,  H01L2224/05599

摘要： With a microwave FET, an incorporated Schottky junction capacitance or PN junction capacitance is small and such a junction is weak against static electricity. However, with a microwave device, the method of connecting a protecting diode cannot be used since this method increases the parasitic capacitance and causes degradation of the high-frequency characteristics. In order to solve the above problems, a protecting element, having a first n+-type region-insulating region-second n+-type region arrangement is connected in parallel between two terminals of a protected element having a PN junction, Schottky junction, or capacitor. Since discharge can be performed between the first and second n+ regions that are adjacent each other, electrostatic energy that would reach the operating region of an FET can be attenuated without increasing the parasitic capacitance.

摘要翻译： 使用微波FET，结合的肖特基结电容或PN结电容小，并且这种结对静电弱。 然而，利用微波装置，不能使用连接保护二极管的方法，因为这种方法增加了寄生电容并导致高频特性的劣化。 为了解决上述问题，具有第一n +型区域 - 第二n +型区域布置的保护元件并联连接在具有PN结，肖特基结或电容器的受保护元件的两个端子之间 。 由于可以在彼此相邻的第一和第二n +区之间进行放电，所以可以在不增加寄生电容的情况下衰减到达FET工作区域的静电能量。

公开(公告)号：US06737890B2

公开(公告)日：2004-05-18

申请号：US10073363

申请日：2002-02-13

申请人： Toshikazu Hirai ,  Tetsuro Asano

发明人： Toshikazu Hirai ,  Tetsuro Asano

IPC分类号： H03K17693

CPC分类号： H01L27/0605 ,  H01L23/4824 ,  H01L2924/0002 ,  H03K17/693 ,  H03K2217/0036 ,  H01L2924/00

摘要： A switching circuit device has a first FET and a second FET, and operates with single control terminal. The device also has a common input terminal connected to the drain or source electrode of the two FETs, a first output terminal and a second output terminal connected to the source or the drain electrode of the respective FET, a bias element applying an bias to the first output terminal, a first connection connecting the control terminal to the second FET, a second connection connecting the gate of the second FET to the ground, and a direct current isolation element placed between the two FETs.

摘要翻译： 开关电路器件具有第一FET和第二FET，并且具有单个控制端子。 该器件还具有连接到两个FET的漏极或源电极的公共输入端子，连接到相应FET的源极或漏极的第一输出端子和第二输出端子，偏置元件施加偏压 第一输出端子，将控制端子连接到第二FET的第一连接，将第二FET的栅极连接到地的第二连接，以及放置在两个FET之间的直流隔离元件。

公开(公告)号：US06946891B2

公开(公告)日：2005-09-20

申请号：US10781941

申请日：2004-02-20

申请人： Tetsuro Asano ,  Mikito Sakakibara ,  Toshikazu Hirai

发明人： Tetsuro Asano ,  Mikito Sakakibara ,  Toshikazu Hirai

IPC分类号： H01L27/04 ,  H01L21/06 ,  H01L21/338 ,  H01L21/66 ,  H01L21/822 ,  H01L21/8232 ,  H01L27/02 ,  H01L27/06 ,  H01L29/80 ,  H01L29/812 ,  H02H9/00 ,  H03K5/08 ,  H03K17/00 ,  H03K17/16 ,  H03K17/693

CPC分类号： H01L27/0288 ,  B82Y30/00 ,  H01L51/426 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2924/12032 ,  H01L2924/00

摘要： Since improvement measures are not taken in regard to the electrostatic breakdown voltage, electrostatic breakdown voltages, between the common input terminal IN—first control terminal Ctl-1, between the common input terminal IN—second control terminal Ctl-2, between the first control terminal Ctl-1—the first output terminal OUT1, and between the second control terminal Ctl-2—the second output terminal OUT2, where both ends of gate Schottky junctions of FETs are lead out to the exterior, are low. To solve the problem, the embodiment of the invention provides a switch circuit device, wherein protecting elements are connected by disposing two electrode pads, for connection to a single control terminal, on a chip and positioning the electrode pads near the common input terminal pad I and an output terminal pad O1 or O2. The electrostatic energies that are applied between the first output terminal OUT1—the first control terminal Ctl-1, between the common input terminal IN—the first control terminal Ctl-1, between the second output terminal OUT2—the second control terminal Ctl-2, and between the common input terminal IN—the second control terminal Ctl-2 can be respectively attenuated to the same degree and most efficiently.

摘要翻译： 由于在公共输入端子IN-first控制端子Ct1-1之间的公共输入端子IN-第二控制端子Ctl-2之间的静电击穿电压，静电击穿电压之间的静电击穿电压不在第一控制 端子Ctl-1-第一输出端子OUT 1和第二控制端子Ct1-2-第二输出端子OUT2之间的第二输出端子OUT 2，其中FET的栅极肖特基结的两端都被引出到外部。 为了解决这个问题，本发明的实施例提供一种开关电路装置，其中保护元件通过在芯片上设置用于连接到单个控制端子的两个电极焊盘连接，并将电极焊盘定位在公共输入端子焊盘I附近 和输出端子焊盘O 1或O 2。 施加在第一输出端子OUT 1之间的第一控制端子Ct1-1之间的公共输入端子IN-第一控制端子Ct1-1之间的第二输出端子OUT 2之间的静电能量 - 第二控制端子Ct1 -2，并且在公共输入端子IN-第二控制端子Ct1-2之间可以分别以相同的程度和最有效地衰减。

公开(公告)号：US06657266B2

公开(公告)日：2003-12-02

申请号：US10073364

申请日：2002-02-13

申请人： Toshikazu Hirai ,  Tetsuro Asano

发明人： Toshikazu Hirai ,  Tetsuro Asano

IPC分类号： H01L29732

CPC分类号： H03K17/693 ,  H01L23/4824 ,  H01L23/49503 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0605 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48237 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/4912 ,  H01L2224/49171 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/0102 ,  H01L2924/01037 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12032 ,  H01L2924/13063 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/181 ,  H01L2924/19041 ,  H03K2217/0036 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： A switching circuit device has a first FET and a second FET, and operates with single control terminal. The device also has a common input terminal connected to the drain or source electrode of the two FETs, a first output terminal and a second output terminal connected to the source or the drain electrode of the respective FET, a bias element applying an bias to the first output terminal, a first connection connecting the control terminal to the second FET, a second connection connecting the gate of the second FET to the ground, and a direct current isolation element placed between the two FETs. The device is housed in a MCP6 package with six pins.

公开(公告)号：US06627956B2

公开(公告)日：2003-09-30

申请号：US10163873

申请日：2002-06-07

申请人： Tetsuro Asano ,  Toshikazu Hirai ,  Mikito Sakakibara

发明人： Tetsuro Asano ,  Toshikazu Hirai ,  Mikito Sakakibara

IPC分类号： H01L2362

CPC分类号： H01L27/0605 ,  H03K17/04106

摘要： A semiconductor switching device of mirror logic includes two FETs having a gate width of 600 &mgr;m, a common input terminal, two control terminal and two output terminals. The resistors connecting the control terminals and the gate electrodes of FETs are placed underneath a pad metal layer extending from the common input terminal. Both FETs extend into the space between the control terminals and the output terminals. The device can be housed in the same package as the device of non-mirror logic.