公开(公告)号：US5514425A

公开(公告)日：1996-05-07

申请号：US392737

申请日：1995-03-06

申请人： Hitoshi Ito ,  Kyoichi Suguro ,  Nobuo Hayasaka ,  Haruo Okano ,  Shinji Himori ,  Kazuya Nagaseki ,  Syuji Mochizuki

发明人： Hitoshi Ito ,  Kyoichi Suguro ,  Nobuo Hayasaka ,  Haruo Okano ,  Shinji Himori ,  Kazuya Nagaseki ,  Syuji Mochizuki

IPC分类号： H01L21/205 ,  C23C16/04 ,  C23C16/34 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/768 ,  C23C14/02

CPC分类号： H01L21/76865 ,  C23C16/045 ,  C23C16/34 ,  H01L21/76843 ,  H01L21/76877

摘要： A thin film-forming method according to the present invention is characterized by comprising the steps of introducing TiCl.sub.4, hydrogen, nitrogen and NF.sub.3 into a film-forming chamber containing a semiconductor substrate (1) having a groove made in its surface, after the chamber has been evacuated to 10.sup.-4 Torr or less; and converting these gases into plasma, thereby forming a thin TiN film on only that portion of the groove which is other than the wall surfaces of the groove.

摘要翻译： PCT No.PCT / JP94 / 01089 Sec。 371日期：1995年3月6日 102（e）1995年3月6日PCT PCT 1994年7月5日PCT公布。 第WO95 / 02076号公报 日本1990年1月19日。根据本发明的薄膜形成方法的特征在于包括以下步骤：将TiCl 4，氢，氮和NF 3引入包含具有凹槽的半导体衬底（1）的成膜室 在其表面上，在室被抽真空至10-4乇或更小之后; 并将这些气体转化为等离子体，从而在凹槽的除了凹槽的壁表面之外的部分上形成薄的TiN膜。

公开(公告)号：US5424246A

公开(公告)日：1995-06-13

申请号：US99695

申请日：1993-07-30

申请人： Mie Matsuo ,  Haruo Okano ,  Nobuo Hayasaka ,  Kyoichi Suguro ,  Hideshi Miyajima ,  Jun-ichi Wada

发明人： Mie Matsuo ,  Haruo Okano ,  Nobuo Hayasaka ,  Kyoichi Suguro ,  Hideshi Miyajima ,  Jun-ichi Wada

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/528 ,  H01L23/532 ,  H01L21/205

CPC分类号： H01L21/76877 ,  H01L21/28518 ,  H01L21/76823 ,  H01L21/76838 ,  H01L21/76849 ,  H01L23/5283 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/12044

摘要： According to this invention, there is provided a method of forming a groove wiring layer, including the steps of forming a metal oxide film, consisting of a metal oxide having a decrease in standard free energy smaller than a decrease in standard free energy of a hydrogen oxide or of a carbon oxide, on an insulating film formed on a semiconductor substrate, and reducing the metal oxide film to form an electrode-wiring layer consisting of a metal which is a main component constituting the metal oxide. In this manner, an electrode-wiring layer having high EM and SM resistances without causing an increase in electric resistivity caused by an impurity or the like can be obtained.

摘要翻译： 根据本发明，提供一种形成沟槽布线层的方法，包括形成金属氧化物膜的步骤，该金属氧化物膜由标准自由能降低的金属氧化物组成，其小于氢的标准自由能的降低 氧化物或碳氧化物，在形成于半导体衬底上的绝缘膜上，还原金属氧化物膜，形成由作为构成金属氧化物的主要成分的金属构成的电极配线层。 以这种方式，可以获得具有高EM和SM电阻而不引起由杂质引起的电阻率增加的电极布线层等。

公开(公告)号：US5731634A

公开(公告)日：1998-03-24

申请号：US659389

申请日：1996-06-06

申请人： Mie Matsuo ,  Haruo Okano ,  Nobuo Hayasaka ,  Kyoichi Suguro ,  Hideshi Miyajima ,  Jun-ichi Wada

发明人： Mie Matsuo ,  Haruo Okano ,  Nobuo Hayasaka ,  Kyoichi Suguro ,  Hideshi Miyajima ,  Jun-ichi Wada

IPC分类号： H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76877 ,  H01L21/28518 ,  H01L21/76823 ,  H01L21/76838 ,  H01L21/76849 ,  H01L23/5283 ,  H01L23/53238 ,  H01L2924/0002

摘要： The present invention provides a method of manufacturing a semiconductor device, including the steps of forming a metal oxide film made of a metal oxide having a decrease in standard free energy smaller than a decrease in standard free energy of hydrogen oxide or of carbon oxide, on an insulating film formed on a semiconductor substrate, forming a metal oxide film pattern by subjecting a treatment to the metal oxide film, and converting said metal oxide pattern into at least one of an electrode and a wiring made of a metal which is a main component constituting the metal oxide, by reducing the metal oxide film pattern at a temperature of 80.degree. to 500.degree. C.

摘要翻译： 本发明提供了一种制造半导体器件的方法，包括以下步骤：形成由金属氧化物制成的金属氧化物膜，其标准自由能的降低小于氧化物或氧化碳的标准自由能的降低，对 形成在半导体基板上的绝缘膜，通过对金属氧化物膜进行处理形成金属氧化物膜图案，并将所述金属氧化物图案转换成电极和由作为主要成分的金属制成的布线中的至少一个 通过在80℃〜500℃的温度下还原金属氧化物膜图案来构成金属氧化物。

公开(公告)号：US5661345A

公开(公告)日：1997-08-26

申请号：US353214

申请日：1994-12-01

申请人： Junichi Wada ,  Hisashi Kaneko ,  Kyoichi Suguro ,  Nobuo Hayasaka ,  Haruo Okano

发明人： Junichi Wada ,  Hisashi Kaneko ,  Kyoichi Suguro ,  Nobuo Hayasaka ,  Haruo Okano

IPC分类号： H01L21/3205 ,  H01L21/285 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/48

CPC分类号： H01L23/53223 ,  H01L21/28512 ,  H01L21/76882 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002

摘要： The method of producing a semiconductor device includes the steps of forming a groove having a predetermined pattern shape on the surface of a substrate; forming a metal film on the substrate while reaction with the surface of the substrate is suppressed; and agglomerating the metal film by in-situ annealing, wherein agglomeration of the metal film is started before the metal film reacts with the surface of the substrate due to annealing, while formation of a native oxide on the metal film is suppressed, and whereby the metal film is filled into the groove by annealing at a predetermined temperature for a predetermined period of time. The structure of the semiconductor device includes an insulator in which there is formed a groove portion having a predetermined pattern shape and an electrode interconnection made of a single-crystal metal which is filled in the groove portion.

摘要翻译： 制造半导体器件的方法包括以下步骤：在衬底的表面上形成具有预定图案形状的沟槽; 在与基板的表面反应的同时，在基板上形成金属膜; 并且通过原位退火使金属膜凝聚，其中金属膜在金属膜由于退火而与基板的表面反应之前开始凝聚，同时在金属膜上形成天然氧化物被抑制， 通过在预定温度下退火预定时间将金属膜填充到槽中。 半导体器件的结构包括绝缘体，其中形成有预定图案形状的沟槽部分和由填充在沟槽部分中的单晶金属制成的电极互连。

公开(公告)号：US5561082A

公开(公告)日：1996-10-01

申请号：US405948

申请日：1995-03-17

申请人： Mie Matsuo ,  Haruo Okano ,  Nobuo Hayasaka ,  Kyoichi Suguro ,  Hideshi Miyajima ,  Jun-ichi Wada

发明人： Mie Matsuo ,  Haruo Okano ,  Nobuo Hayasaka ,  Kyoichi Suguro ,  Hideshi Miyajima ,  Jun-ichi Wada

IPC分类号： H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L21/28

CPC分类号： H01L21/76877 ,  H01L21/28518 ,  H01L21/76823 ,  H01L21/76838 ,  H01L21/76849 ,  H01L23/5283 ,  H01L23/53238 ,  H01L2924/0002

摘要： The present invention provides a method of manufacturing a semiconductor device, including the steps of forming a metal oxide film made of a metal oxide having a decrease in standard free energy smaller than a decrease in standard free energy of hydrogen oxide or of carbon oxide, on an insulating film formed on a semiconductor substrate, forming a metal oxide film pattern by subjecting a treatment to the metal oxide film, and converting said metal oxide pattern into at least one of an electrode and a wiring made of a metal which is a main component constituting the metal oxide, by reducing the metal oxide film pattern at a temperature of 80.degree. to 500.degree. C.

摘要翻译： 本发明提供了一种制造半导体器件的方法，包括以下步骤：形成由金属氧化物制成的金属氧化物膜，其标准自由能的降低小于氧化物或氧化碳的标准自由能的降低，对 形成在半导体基板上的绝缘膜，通过对金属氧化物膜进行处理形成金属氧化物膜图案，并将所述金属氧化物图案转换成电极和由作为主要成分的金属制成的布线中的至少一个 通过在80℃〜500℃的温度下还原金属氧化物膜图案来构成金属氧化物。

公开(公告)号：US5409862A

公开(公告)日：1995-04-25

申请号：US035208

申请日：1993-03-22

申请人： Junichi Wada ,  Hisashi Kaneko ,  Kyoichi Suguro ,  Nobuo Hayasaka ,  Haruo Okano

发明人： Junichi Wada ,  Hisashi Kaneko ,  Kyoichi Suguro ,  Nobuo Hayasaka ,  Haruo Okano

IPC分类号： H01L21/3205 ,  H01L21/285 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/44

CPC分类号： H01L23/53223 ,  H01L21/28512 ,  H01L21/76882 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002

摘要： The method of producing a semiconductor device includes the steps of forming a groove having a predetermined pattern shape on the surface of a substrate; forming a metal film on the substrate while reaction with the surface of the substrate is suppressed; and agglomerating the metal film by in-situ annealing, wherein agglomeration of the metal film is started before the metal film reacts with the surface of the substrate due to annealing, while formation of a native oxide on the metal film is suppressed, and whereby the metal film is filled into the groove by annealing at a predetermined temperature for a predetermined period of time. The structure of the semiconductor device includes an insulator in which there is formed a groove portion having a predetermined pattern shape and an electrode interconnection made of a single-crystal metal which is filled in the groove portion.

摘要翻译： 制造半导体器件的方法包括以下步骤：在衬底的表面上形成具有预定图案形状的沟槽; 在与基板的表面反应的同时，在基板上形成金属膜; 并且通过原位退火使金属膜凝聚，其中金属膜在金属膜由于退火而与基板的表面反应之前开始凝聚，同时在金属膜上形成天然氧化物被抑制， 通过在预定温度下退火预定时间将金属膜填充到槽中。 半导体器件的结构包括绝缘体，其中形成有预定图案形状的沟槽部分和由填充在沟槽部分中的单晶金属制成的电极互连。

公开(公告)号：US5641581A

公开(公告)日：1997-06-24

申请号：US411994

申请日：1995-03-28

申请人： Yukio Nishiyama ,  Rempei Nakata ,  Nobuo Hayasaka ,  Haruo Okano ,  Riichirou Aoki ,  Takahito Nagamatsu ,  Akemi Satoh ,  Masao Toyosaki ,  Hitoshi Ito

发明人： Yukio Nishiyama ,  Rempei Nakata ,  Nobuo Hayasaka ,  Haruo Okano ,  Riichirou Aoki ,  Takahito Nagamatsu ,  Akemi Satoh ,  Masao Toyosaki ,  Hitoshi Ito

IPC分类号： C23C16/40 ,  H01L21/31 ,  H01L21/311 ,  H01L21/316 ,  H01L21/768 ,  H01L23/532 ,  B32B9/00

CPC分类号： H01L21/02274 ,  H01L21/02131 ,  H01L21/0214 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/31111 ,  H01L21/31625 ,  H01L21/31629 ,  H01L21/76801 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002

摘要： Disclosed is a method of manufacturing a semiconductor device, in which a silicon oxide film containing fluorine, said film exhibiting a low dielectric constant and a low hygroscopicity and acting as an insulating film for electrically isolating wirings included in a semiconductor device, is formed by a plasma CVD method using a source gas containing at least silicon, oxygen and fluorine, under the conditions that the relationship between the gas pressure P (Torr) and the ion energy E (eV) satisfies formula A given below:P.gtoreq.5.times.10.sup.-4, P.ltoreq.10.sup.-1.times.10.sup.-E/45( A)and the relationship between the ion energy E (eV) and the plasma density D (/cm.sup.3) satisfies the formula B given below:D.gtoreq.2.times.10.sup.11.times.10.sup.-E/45, 10 .ltoreq.E(B)

摘要翻译： 公开了一种制造半导体器件的方法，其中含有氟的氧化硅膜，所述膜具有低介电常数和低吸湿性并且用作用于电绝缘包括在半导体器件中的布线的绝缘膜，其通过 在气体压力P（Torr）和离子能量E（eV）之间的关系满足下面给出的公式A的条件下，使用至少含有硅，氧和氟的源气体的等离子体CVD方法：P> = 5×10- 4，P <= 10-1×10-E / 45（A），离子能E（eV）与等离子体密度D（/ cm 3）之间的关系满足以下公式B：D> / = 2x1011×10-E / 45,10（E）（B）

公开(公告)号：US5429995A

公开(公告)日：1995-07-04

申请号：US94423

申请日：1993-07-16

申请人： Yukio Nishiyama ,  Rempei Nakata ,  Nobuo Hayasaka ,  Haruo Okano ,  Riichirou Aoki ,  Takahito Nagamatsu ,  Akemi Satoh ,  Masao Toyosaki ,  Hitoshi Ito

发明人： Yukio Nishiyama ,  Rempei Nakata ,  Nobuo Hayasaka ,  Haruo Okano ,  Riichirou Aoki ,  Takahito Nagamatsu ,  Akemi Satoh ,  Masao Toyosaki ,  Hitoshi Ito

IPC分类号： C23C16/40 ,  H01L21/31 ,  H01L21/311 ,  H01L21/316 ,  H01L21/768 ,  H01L23/532 ,  H01L21/02

CPC分类号： H01L21/02274 ,  H01L21/02131 ,  H01L21/0214 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/31111 ,  H01L21/31625 ,  H01L21/31629 ,  H01L21/76801 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002

摘要： Disclosed is a method of manufacturing a semiconductor device, in which a silicon oxide film containing fluorine, said film exhibiting a low dielectric constant and a low hygroscopicity and acting as an insulating film for electrically isolating wirings included in a semiconductor device, is formed by a plasma CVD method using a source gas containing at least silicon, oxygen and fluorine, under the conditions that the relationship between the gas pressure P (Torr) and the ion energy E (eV) satisfies formula A given below:P.gtoreq.5.times.10.sup.-4,P.ltoreq.10.sup.-1 .times.10.sup.-E/45(A)and the relationship between the ion energy E (ev) and the plasma density D (/cm.sup.3) satisfies the formula B given below:D.gtoreq.2.times.10.sup.11 .times.10.sup.-E/45, 10.ltoreq.E(B)

摘要翻译： 公开了一种制造半导体器件的方法，其中含有氟的氧化硅膜，所述膜具有低介电常数和低吸湿性并且用作用于电绝缘包括在半导体器件中的布线的绝缘膜，其通过 在气体压力P（Torr）和离子能量E（eV）之间的关系满足下面给出的公式A的条件下，使用至少含有硅，氧和氟的源气体的等离子体CVD方法：P> = 5×10- 如图4所示，P / = 2x1011×10-E / 45,10（E）（B）

公开(公告)号：US06306756B1

公开(公告)日：2001-10-23

申请号：US09580922

申请日：2000-05-26

申请人： Masahiko Hasunuma ,  Sachiyo Ito ,  Keizo Shimamura ,  Hisashi Kaneko ,  Nobuo Hayasaka ,  Junsei Tsutsumi ,  Akihiro Kajita ,  Junichi Wada ,  Haruo Okano

发明人： Masahiko Hasunuma ,  Sachiyo Ito ,  Keizo Shimamura ,  Hisashi Kaneko ,  Nobuo Hayasaka ,  Junsei Tsutsumi ,  Akihiro Kajita ,  Junichi Wada ,  Haruo Okano

IPC分类号： H01L214763

CPC分类号： H01L21/76882

摘要： A method for the production of a semiconductor device having an electrode line formed in a semiconducting substrate is disclosed which comprises preparing a semiconducting substrate having trenches and/or contact holes formed preparatorily in a region destined to form the electrode line, forming a conductive film formed mainly of at least one member selected from among Cu, Ag, and Au on the surface of the semiconducting substrate, heat-treating the superposed Cu film while supplying at least an oxidizing gas thereto thereby flowing the Cu film and causing never melting to fill the trenches and/or contact holes, and removing by polishing the part of the conductive film which falls outside the region of the electrode line and completing the electrode lines consequently. During the heat treatment, a reducing gas is supplied in addition to the oxidizing gas to induce a local oxidation-reduction reaction and fluidify and/or flow the conductive film and consequently accomplish the embodiment of the conductive film in the trenches. The formation of the interconnection is also accomplished by forming a conductive film on the surface of a semiconducting substrate having trenches formed therein, exerting thereon uniaxial stress from above the semiconducting substrate, heat treating the formed conductive film thereby flowing the conductive film, to fill the trenches, and polishing the surface of the semiconducting substrate.

摘要翻译： 公开了一种制造半导体器件的方法，该半导体器件具有形成在半导体衬底中的电极线，其包括制备半导体衬底，该半导体衬底具有在预定形成电极线的区域中预先形成的沟槽和/或接触孔，形成导电膜 主要是在半导体基板的表面上选自Cu，Ag和Au中的至少一个元件，在至少供给氧化气体的同时对叠加的Cu膜进行热处理，从而使Cu膜流动，从而不会熔化以填充 沟槽和/或接触孔，并且通过抛光导电膜的掉落在电极线的区域外部并且完成电极线的部分去除。 在热处理期间，除了氧化气体之外还提供还原气体以引起局部氧化还原反应，并使导电膜流通和/或流动，从而完成沟槽中导电膜的实施例。 互连的形成还可以通过在其上形成有沟槽的半导体衬底的表面上形成导电膜，在半导体衬底上方施加单轴应力，热处理形成的导电膜从而使导电膜流动，从而填充 沟槽，并抛光半导体衬底的表面。

公开(公告)号：US6090701A

公开(公告)日：2000-07-18

申请号：US521088

申请日：1995-06-20

申请人： Masahiko Hasunuma ,  Sachiyo Ito ,  Keizo Shimamura ,  Hisashi Kaneko ,  Nobuo Hayasaka ,  Junsei Tsutsumi ,  Akihiro Kajita ,  Junichi Wada ,  Haruo Okano

发明人： Masahiko Hasunuma ,  Sachiyo Ito ,  Keizo Shimamura ,  Hisashi Kaneko ,  Nobuo Hayasaka ,  Junsei Tsutsumi ,  Akihiro Kajita ,  Junichi Wada ,  Haruo Okano

IPC分类号： H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76882

摘要： A method for the production of a semiconductor device having an electrode line formed in a semiconducting substrate is disclosed which comprises preparing a semiconducting substrate having trenches and/or contact holes formed preparatorily in a region destined to form the electrode line, forming a conductive film formed mainly of at least one member selected from among Cu, Ag, and Au on the surface of the semiconducting substrate, heat-treating the superposed Cu film while supplying at least an oxidizing gas thereto thereby flowing the Cu film to fill the trenches and/or contact holes, and removing by polishing the part of the conductive film which falls outside the region of the electrode line and completing the electrode lines consequently. During the heat treatment, a reducing gas is supplied in addition to the oxidizing gas to induce a local oxidation-reduction reaction and fluidify and/or flow the conductive film and consequently accomplish the embodiment of the conductive film in the trenches.

摘要翻译： 公开了一种制造半导体器件的方法，该半导体器件具有形成在半导体衬底中的电极线，其包括制备半导体衬底，该半导体衬底具有在预定形成电极线的区域中预先形成的沟槽和/或接触孔，形成导电膜 主要是在半导体基板的表面上选自Cu，Ag和Au中的至少一个元件，在至少供给氧化气体的同时对叠加的Cu膜进行热处理，从而使Cu膜流过以填充沟槽和/或 接触孔，并且通过抛光导电膜的掉在电极线的区域外部并且完成电极线的部分去除。 在热处理期间，除了氧化气体之外还提供还原气体以引起局部氧化还原反应，并使导电膜流通和/或流动，从而完成沟槽中导电膜的实施例。