公开(公告)号：US5514425A

公开(公告)日：1996-05-07

申请号：US392737

申请日：1995-03-06

申请人： Hitoshi Ito ,  Kyoichi Suguro ,  Nobuo Hayasaka ,  Haruo Okano ,  Shinji Himori ,  Kazuya Nagaseki ,  Syuji Mochizuki

发明人： Hitoshi Ito ,  Kyoichi Suguro ,  Nobuo Hayasaka ,  Haruo Okano ,  Shinji Himori ,  Kazuya Nagaseki ,  Syuji Mochizuki

IPC分类号： H01L21/205 ,  C23C16/04 ,  C23C16/34 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/768 ,  C23C14/02

CPC分类号： H01L21/76865 ,  C23C16/045 ,  C23C16/34 ,  H01L21/76843 ,  H01L21/76877

摘要： A thin film-forming method according to the present invention is characterized by comprising the steps of introducing TiCl.sub.4, hydrogen, nitrogen and NF.sub.3 into a film-forming chamber containing a semiconductor substrate (1) having a groove made in its surface, after the chamber has been evacuated to 10.sup.-4 Torr or less; and converting these gases into plasma, thereby forming a thin TiN film on only that portion of the groove which is other than the wall surfaces of the groove.

摘要翻译： PCT No.PCT / JP94 / 01089 Sec。 371日期：1995年3月6日 102（e）1995年3月6日PCT PCT 1994年7月5日PCT公布。 第WO95 / 02076号公报 日本1990年1月19日。根据本发明的薄膜形成方法的特征在于包括以下步骤：将TiCl 4，氢，氮和NF 3引入包含具有凹槽的半导体衬底（1）的成膜室 在其表面上，在室被抽真空至10-4乇或更小之后; 并将这些气体转化为等离子体，从而在凹槽的除了凹槽的壁表面之外的部分上形成薄的TiN膜。

公开(公告)号：US5641581A

公开(公告)日：1997-06-24

申请号：US411994

申请日：1995-03-28

申请人： Yukio Nishiyama ,  Rempei Nakata ,  Nobuo Hayasaka ,  Haruo Okano ,  Riichirou Aoki ,  Takahito Nagamatsu ,  Akemi Satoh ,  Masao Toyosaki ,  Hitoshi Ito

发明人： Yukio Nishiyama ,  Rempei Nakata ,  Nobuo Hayasaka ,  Haruo Okano ,  Riichirou Aoki ,  Takahito Nagamatsu ,  Akemi Satoh ,  Masao Toyosaki ,  Hitoshi Ito

IPC分类号： C23C16/40 ,  H01L21/31 ,  H01L21/311 ,  H01L21/316 ,  H01L21/768 ,  H01L23/532 ,  B32B9/00

CPC分类号： H01L21/02274 ,  H01L21/02131 ,  H01L21/0214 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/31111 ,  H01L21/31625 ,  H01L21/31629 ,  H01L21/76801 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002

摘要： Disclosed is a method of manufacturing a semiconductor device, in which a silicon oxide film containing fluorine, said film exhibiting a low dielectric constant and a low hygroscopicity and acting as an insulating film for electrically isolating wirings included in a semiconductor device, is formed by a plasma CVD method using a source gas containing at least silicon, oxygen and fluorine, under the conditions that the relationship between the gas pressure P (Torr) and the ion energy E (eV) satisfies formula A given below:P.gtoreq.5.times.10.sup.-4, P.ltoreq.10.sup.-1.times.10.sup.-E/45( A)and the relationship between the ion energy E (eV) and the plasma density D (/cm.sup.3) satisfies the formula B given below:D.gtoreq.2.times.10.sup.11.times.10.sup.-E/45, 10 .ltoreq.E(B)

摘要翻译： 公开了一种制造半导体器件的方法，其中含有氟的氧化硅膜，所述膜具有低介电常数和低吸湿性并且用作用于电绝缘包括在半导体器件中的布线的绝缘膜，其通过 在气体压力P（Torr）和离子能量E（eV）之间的关系满足下面给出的公式A的条件下，使用至少含有硅，氧和氟的源气体的等离子体CVD方法：P> = 5×10- 4，P <= 10-1×10-E / 45（A），离子能E（eV）与等离子体密度D（/ cm 3）之间的关系满足以下公式B：D> / = 2x1011×10-E / 45,10（E）（B）

公开(公告)号：US5429995A

公开(公告)日：1995-07-04

申请号：US94423

申请日：1993-07-16

申请人： Yukio Nishiyama ,  Rempei Nakata ,  Nobuo Hayasaka ,  Haruo Okano ,  Riichirou Aoki ,  Takahito Nagamatsu ,  Akemi Satoh ,  Masao Toyosaki ,  Hitoshi Ito

发明人： Yukio Nishiyama ,  Rempei Nakata ,  Nobuo Hayasaka ,  Haruo Okano ,  Riichirou Aoki ,  Takahito Nagamatsu ,  Akemi Satoh ,  Masao Toyosaki ,  Hitoshi Ito

IPC分类号： C23C16/40 ,  H01L21/31 ,  H01L21/311 ,  H01L21/316 ,  H01L21/768 ,  H01L23/532 ,  H01L21/02

CPC分类号： H01L21/02274 ,  H01L21/02131 ,  H01L21/0214 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/31111 ,  H01L21/31625 ,  H01L21/31629 ,  H01L21/76801 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002

摘要： Disclosed is a method of manufacturing a semiconductor device, in which a silicon oxide film containing fluorine, said film exhibiting a low dielectric constant and a low hygroscopicity and acting as an insulating film for electrically isolating wirings included in a semiconductor device, is formed by a plasma CVD method using a source gas containing at least silicon, oxygen and fluorine, under the conditions that the relationship between the gas pressure P (Torr) and the ion energy E (eV) satisfies formula A given below:P.gtoreq.5.times.10.sup.-4,P.ltoreq.10.sup.-1 .times.10.sup.-E/45(A)and the relationship between the ion energy E (ev) and the plasma density D (/cm.sup.3) satisfies the formula B given below:D.gtoreq.2.times.10.sup.11 .times.10.sup.-E/45, 10.ltoreq.E(B)

摘要翻译： 公开了一种制造半导体器件的方法，其中含有氟的氧化硅膜，所述膜具有低介电常数和低吸湿性并且用作用于电绝缘包括在半导体器件中的布线的绝缘膜，其通过 在气体压力P（Torr）和离子能量E（eV）之间的关系满足下面给出的公式A的条件下，使用至少含有硅，氧和氟的源气体的等离子体CVD方法：P> = 5×10- 如图4所示，P / = 2x1011×10-E / 45,10（E）（B）

公开(公告)号：US08035214B1

公开(公告)日：2011-10-11

申请号：US09830949

申请日：1999-11-17

申请人： Naohiro Hirose ,  Hitoshi Ito ,  Yoshiyuki Iwata ,  Masanori Kawade ,  Hajime Yazu

发明人： Naohiro Hirose ,  Hitoshi Ito ,  Yoshiyuki Iwata ,  Masanori Kawade ,  Hajime Yazu

IPC分类号： H01L23/48 ,  H01L21/4763

CPC分类号： H01L23/49811 ,  H01L2224/05001 ,  H01L2224/05572 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2924/00013 ,  H01L2924/01019 ,  H01L2924/01322 ,  H01L2924/15312 ,  H05K1/111 ,  H05K1/112 ,  H05K3/28 ,  H05K3/321 ,  H05K3/3421 ,  H05K3/384 ,  H05K3/4602 ,  H05K2201/09381 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/0979 ,  H05K2201/10318 ,  Y10T428/239

摘要： A package substrate 310 incorporating a substrate provided with a conductor layer 5, a conductive connecting pin 100 arranged to establish the electrical connection with a mother board and secured to the surface of the substrate, wherein a pad 16 for securing the conductive connecting pin is provided for the package substrate 310. The pad 16 is covered with an organic resin insulating layer 15 having an opening 18 through which the pad 16 is partially exposed to the outside. The conductive connecting pin 100 is secured to the pad exposed to the outside through the opening with a conductive adhesive agent 17 so that solution of the conductive connecting pin 100 from the substrate occurring, for example when mounting is performed is prevented.

摘要翻译： 一种包含衬底的封装衬底310，该衬底设置有导体层5，导电连接销100被布置成与母板建立电连接并固定到衬底的表面，其中提供用于固定导电连接销的衬垫16 用于封装衬底310.衬垫16被具有开口18的有机树脂绝缘层15覆盖，衬垫16通过该开口部分地暴露于外部。 导电连接销100通过导电粘合剂17通过开口固定到暴露于外部的焊盘，从而防止例如当执行安装时发生例如导电连接销100从基板的溶液。

公开(公告)号：US20100032200A1

公开(公告)日：2010-02-11

申请号：US12581205

申请日：2009-10-19

申请人： Naohiro HIROSE ,  Hitoshi Ito ,  Yoshiyuki Iwata ,  Masanori Kawade ,  Hajime Yazu

发明人： Naohiro HIROSE ,  Hitoshi Ito ,  Yoshiyuki Iwata ,  Masanori Kawade ,  Hajime Yazu

IPC分类号： H05K1/11

CPC分类号： H01L23/49811 ,  H01L2224/05001 ,  H01L2224/05572 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2924/00013 ,  H01L2924/01019 ,  H01L2924/01322 ,  H01L2924/15312 ,  H05K1/111 ,  H05K1/112 ,  H05K3/28 ,  H05K3/321 ,  H05K3/3421 ,  H05K3/384 ,  H05K3/4602 ,  H05K2201/09381 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/0979 ,  H05K2201/10318 ,  Y10T428/239

摘要： A package substrate 310 incorporating a substrate provided with a conductor layer 5, a conductive connecting pin 100 arranged to establish the electrical connection with a motherboard and secured to the surface of the substrate, wherein a pad 16 for securing the conductive connecting pin is provided for the package substrate 310. The pad 16 is covered with an organic resin insulating layer 15 having an opening 18 through which the pad 16 is partially exposed to the outside. The conductive connecting pin 100 is secured to the pad exposed to the outside through the opening with a conductive adhesive agent 17 so that solution of the conductive connecting pin 100 from the substrate occurring, for example when mounting is performed is prevented.

摘要翻译： 一种包含衬底的封装衬底310，该衬底设置有导体层5，导电连接销100被布置成与主板建立电连接并固定到衬底的表面，其中提供用于固定导电连接销的焊盘16，用于 封装衬底310.衬垫16被具有开口18的有机树脂绝缘层15覆盖，衬垫16通过该开口局部暴露于外部。 导电连接销100通过导电粘合剂17通过开口固定到暴露于外部的焊盘，从而防止例如当执行安装时发生例如导电连接销100从基板的溶液。

公开(公告)号：US07064028B2

公开(公告)日：2006-06-20

申请号：US10959661

申请日：2004-10-07

申请人： Eiji Ito ,  Hitoshi Ito

发明人： Eiji Ito ,  Hitoshi Ito

IPC分类号： H01L21/8234 ,  H01L21/20 ,  H01L21/8242

CPC分类号： H01L27/10852 ,  H01L27/0207 ,  H01L28/91

摘要： A semiconductor memory incorporates cylinder-type stacked capacitors. Each capacitor has a lower electrode and an upper electrode facing each other via a dielectric film. The lower electrode of each capacitor is supported by a beam-like insulator at a side portion of the electrode, the side portion being apart from a lower edge of the lower electrode.

公开(公告)号：US6120772A

公开(公告)日：2000-09-19

申请号：US169193

申请日：1998-10-08

申请人： Hitoshi Ito ,  Toshimitsu Sumiya

发明人： Hitoshi Ito ,  Toshimitsu Sumiya

IPC分类号： A01N65/00 ,  A61K36/06 ,  A61P31/18 ,  A61K35/78

CPC分类号： A61K36/07

摘要： Oral drugs for treating AIDS patients contain water-soluble mixed components contained in cultured mycelia or a culture filtrate solution of Himematsutake (Agaricus blazei).

摘要翻译： 用于治疗艾滋病患者的口服药物含有培养的菌丝体中含有的水溶性混合组分或Himematsutake（Agaricus blazei）的培养滤液。

公开(公告)号：US4923764A

公开(公告)日：1990-05-08

申请号：US91650

申请日：1987-09-01

申请人： Kouji Hirose ,  Hitoshi Ito ,  Kazuhito Yoshida

发明人： Kouji Hirose ,  Hitoshi Ito ,  Kazuhito Yoshida

IPC分类号： C23C14/06 ,  C23C30/00

CPC分类号： C23C30/00 ,  C23C14/0688 ,  Y10T428/12611 ,  Y10T428/12847 ,  Y10T428/12944

摘要： An article having a colored surface comprises an article having a working surface and a coating applied on the working surface comprising a cermet composed of alumina and one of chromium and nichrome and exhibiting a black silver color.

摘要翻译： 具有着色表面的制品包括具有工作表面的物品和施加在工作表面上的包含由氧化铝和铬和镍铬合金之一并呈现黑色银色的金属陶瓷的涂层。

公开(公告)号：US20120032246A1

公开(公告)日：2012-02-09

申请号：US13196084

申请日：2011-08-02

申请人： Masashi HONDA ,  Hitoshi Ito ,  Hideyuki Kinoshita

发明人： Masashi HONDA ,  Hitoshi Ito ,  Hideyuki Kinoshita

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/7881 ,  H01L27/11526 ,  H01L27/11529 ,  H01L29/40114

摘要： A nonvolatile semiconductor memory device according to an embodiment includes a semiconductor substrate, a memory cell transistor formed in a memory cell region, and a field-effect transistor formed in a peripheral circuit region. The memory cell transistor includes: a floating gate electrode; a first inter-electrode insulating film; and a control gate electrode. The field-effect transistor includes: a lower gate electrode; a second inter-electrode insulating film having an opening; and an upper gate electrode electrically connected to the lower gate electrode via the opening. The control gate electrode and the upper gate electrode are formed by a plurality of conductive films that are stacked. The control gate electrode and the upper gate electrode include a barrier film formed in one of interfaces between the stacked conductive films and configured to suppress diffusion of metal atoms. The control gate electrode and the upper gate electrode have a part that is silicided.

摘要翻译： 根据实施例的非易失性半导体存储器件包括形成在存储单元区域中的半导体衬底，存储单元晶体管和形成在外围电路区域中的场效应晶体管。 存储单元晶体管包括：浮栅电极; 第一电极间绝缘膜; 和控制栅电极。 场效应晶体管包括：下栅电极; 具有开口的第二电极间绝缘膜; 以及通过所述开口电连接到所述下栅电极的上栅电极。 控制栅极电极和上部栅极电极由堆叠的多个导电膜形成。 控制栅电极和上栅电极包括形成在层叠导电膜之间的界面之一中的阻挡膜，并且被构造成抑制金属原子的扩散。 控制栅极电极和上部栅电极具有被硅化的部分。

公开(公告)号：US20100096682A1

公开(公告)日：2010-04-22

申请号：US12556242

申请日：2009-09-09

申请人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kito ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Yosuke Komori ,  Megumi Ishiduki ,  Akihiro Nitayama ,  Hideaki Aochi ,  Hitoshi Ito ,  Yasuyuki Matsuoka

发明人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kito ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Yosuke Komori ,  Megumi Ishiduki ,  Akihiro Nitayama ,  Hideaki Aochi ,  Hitoshi Ito ,  Yasuyuki Matsuoka

IPC分类号： H01L29/78 ,  H01L21/768

CPC分类号： H01L27/11578 ,  H01L27/11565 ,  H01L27/11582

摘要： A non-volatile semiconductor storage device has a memory string including a plurality of electrically rewritable memory cells connected in series. The non-volatile semiconductor storage device also has a protruding layer formed to protrude upward with respect to a substrate. The memory string includes: a plurality of first conductive layers laminated on the substrate; a first semiconductor layer formed to penetrate the plurality of first conductive layers; and an electric charge storage layer formed between the first conductive layers and the first semiconductor layer, and configured to be able to store electric charges. Each of the plurality of first conductive layers includes: a bottom portion extending in parallel to the substrate; and a side portion extending upward with respect to the substrate along the protruding layer at the bottom portion. The protruding layer has a width in a first direction parallel to the substrate that is less than or equal to its length in a lamination direction.

摘要翻译： 非易失性半导体存储装置具有串联连接的多个电可重写存储单元的存储串。 非挥发性半导体存储装置还具有形成为相对于基板向上突出的突出层。 存储器串包括：层叠在基板上的多个第一导电层; 形成为穿透所述多个第一导电层的第一半导体层; 以及形成在第一导电层和第一半导体层之间的电荷存储层，并且能够存储电荷。 多个第一导电层中的每一个包括：平行于基板延伸的底部; 以及沿底部的突出层相对于基板向上延伸的侧部。 该突出层在平行于基板的第一方向上的宽度小于或等于其在层叠方向上的长度。