公开(公告)号：US20060237799A1

公开(公告)日：2006-10-26

申请号：US11112768

申请日：2005-04-21

申请人： Hongquiang Lu ,  Peter Burke ,  Wilbur Catabay

发明人： Hongquiang Lu ,  Peter Burke ,  Wilbur Catabay

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： G11C23/00 ,  B82Y10/00 ,  G11C13/025 ,  H01L51/0048 ,  H01L51/0052

摘要： The present invention is directed to structures and methods of fabricating nanotube electromechanical memory cells having a bottom electrode with a substantially planar contact surface. The bottom electrode is configured so that during the operation of the memory cell the nanotube crossbar of the cell can make contact with a substantially planar surface of the bottom electrode.

摘要翻译： 本发明涉及制造具有基本平坦的接触表面的底部电极的纳米管机电存储单元的结构和方法。 底部电极被配置为使得在存储器单元的操作期间，电池的纳米管横截面可以与底部电极的基本平坦的表面接触。

公开(公告)号：US20050208758A1

公开(公告)日：2005-09-22

申请号：US11131003

申请日：2005-05-16

申请人： Hong-Qiang Lu ,  Peter Burke ,  Wilbur Catabay

发明人： Hong-Qiang Lu ,  Peter Burke ,  Wilbur Catabay

IPC分类号： H01L21/312 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L21/02211 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/02315 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/3121 ,  H01L21/76807 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76832 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention is directed to improved dielectric copper barrier layer and related interconnect structures. One structure includes a semiconductor substrate having a copper line. An insulating layer formed of at least one of silicon and carbon is formed on the underlying copper line. An opening is formed in the insulating layer to expose a portion of the copper line. The inner surface of the opening in the insulating layer has a dielectric barrier layer formed thereon to prevent the diffusion of copper into the insulating layer. A copper plug is formed to fill the opening and make electrical contact with the underlying copper interconnect structure. Aspects of the invention also include methods for forming the dielectric copper barrier layers and associate copper interconnects to the underlying copper lines.

摘要翻译： 本发明涉及改进的介电铜阻挡层和相关互连结构。 一种结构包括具有铜线的半导体衬底。 在下面的铜线上形成由硅和碳中的至少一种形成的绝缘层。 在绝缘层中形成开口以露出铜线的一部分。 绝缘层中的开口的内表面具有形成在其上的电介质阻挡层，以防止铜扩散到绝缘层中。 形成铜塞以填充开口并与下面的铜互连结构电接触。 本发明的方面还包括用于形成电介质铜阻挡层和将铜互连连接到下面的铜线的方法。

公开(公告)号：US20050176216A1

公开(公告)日：2005-08-11

申请号：US11106307

申请日：2005-04-14

申请人： Hao Cui ,  Peter Burke ,  Wilbur Catabay

发明人： Hao Cui ,  Peter Burke ,  Wilbur Catabay

IPC分类号： C23C16/32 ,  H01L21/00 ,  H01L21/314 ,  H01L21/46 ,  H01L21/768 ,  H01L29/15

CPC分类号： H01L21/02167 ,  C23C16/325 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/3148 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76826 ,  H01L21/76828

摘要： A method for forming a substantially oxygen-free silicon carbide layer on a substrate, where the silicon carbide layer has a dielectric constant of less than about four. The substrate is held at a deposition temperature of between about zero centigrade and about one hundred centigrade, and a gas flow of tetramethylsilane is introduced at a rate of no more than about one thousand scientific cubic centimeters per minute. The deposition pressure is held between about one milli Torr and about one hundred Torr, and a radio frequency plasma discharge is produced with a power of no more than about two kilowatts. The plasma discharge is halted when a desired thickness of the silicon carbide layer has been formed.

公开(公告)号：US20070190784A1

公开(公告)日：2007-08-16

申请号：US11736402

申请日：2007-04-17

申请人： Hao Cui ,  Peter Burke ,  Wilbur Catabay

发明人： Hao Cui ,  Peter Burke ,  Wilbur Catabay

IPC分类号： H01L21/44

CPC分类号： H01L21/76832 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/76883

摘要： Embodiments of the invention include a copper interconnect structure having increased electromigration lifetime. Such structures can include a semiconductor substrate having a copper layer formed thereon. A dielectric barrier stack is formed on the copper layer. The dielectric barrier stack includes a first portion formed adjacent to the copper layer and a second portion formed on the first portion, the first portion having improved adhesion to copper relative to the second portion and both portions are formed having resistance to copper diffusion. The invention also includes several embodiments for constructing such structures. Adhesion of the dielectric barrier stack to copper can be increased by plasma treating or ion implanting selected portions of the dielectric barrier stack with adhesion enhancing materials to increase the concentration of such materials in the stack.

摘要翻译： 本发明的实施例包括具有增加的电迁移寿命的铜互连结构。 这种结构可以包括其上形成有铜层的半导体衬底。 在铜层上形成介电阻挡层叠体。 电介质势垒叠层包括邻近铜层形成的第一部分和形成在第一部分上的第二部分，第一部分具有相对于第二部分具有改进的铜的粘合性，并且两个部分形成为具有耐铜扩散性。 本发明还包括用于构造这种结构的几个实施例。 可以通过等离子体处理或离子注入电介质阻挡层的选定部分与粘合增强材料来增加电介质阻挡层与铜的附着，以增加堆叠中这种材料的浓度。

公开(公告)号：US20060035457A1

公开(公告)日：2006-02-16

申请号：US10915166

申请日：2004-08-10

申请人： Richard Carter ,  Peter Burke ,  Wilbur Catabay ,  Zhihai Wang ,  Wei-Jen Hsia

发明人： Richard Carter ,  Peter Burke ,  Wilbur Catabay ,  Zhihai Wang ,  Wei-Jen Hsia

IPC分类号： H01L21/4763

CPC分类号： H01L21/76885 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76837

摘要： An improvement to a method of fabricating an integrated circuit. All dielectric material that is laterally surrounding an electrically conductive interconnect is removed, while leaving the dielectric material that directly underlies the electrically conductive interconnect. The electrically conductive interconnect is back filled with a low k material, where the low k material provides low capacitance between laterally adjacent electrically conductive interconnects, and the remaining dielectric material underlying the electrically conductive interconnects provides structural support to the electrically conductive interconnects.

摘要翻译： 对集成电路的制造方法的改进。 移除横向围绕导电互连的所有电介质材料，同时留下直接位于导电互连之下的电介质材料。 导电互连件用低k材料填充，其中低k材料在横向相邻的导电互连之间提供低电容，并且导电互连件下面的剩余电介质材料为导电互连提供结构支撑。

公开(公告)号：US20050090036A1

公开(公告)日：2005-04-28

申请号：US10691400

申请日：2003-10-22

申请人： Hao Cui ,  Peter Burke ,  Wilbur Catabay

发明人： Hao Cui ,  Peter Burke ,  Wilbur Catabay

IPC分类号： C23C16/32 ,  H01L21/00 ,  H01L21/314 ,  H01L21/46 ,  H01L21/768 ,  H01L29/15

CPC分类号： H01L21/02167 ,  C23C16/325 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/3148 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76826 ,  H01L21/76828

摘要： A method for forming a substantially oxygen-free silicon carbide layer on a substrate, where the silicon carbide layer has a dielectric constant of less than about four. The substrate is held at a deposition temperature of between about zero centigrade and about one hundred centigrade, and a gas flow of tetramethylsilane is introduced at a rate of no more than about one thousand scientific cubic centimeters per minute. The deposition pressure is held between about one milli Torr and about one hundred Torr, and a radio frequency plasma discharge is produced with a power of no more than about two kilowatts. The plasma discharge is halted when a desired thickness of the silicon carbide layer has been formed.

摘要翻译： 在基底上形成基本上无氧的碳化硅层的方法，其中碳化硅层的介电常数小于约4。 基板保持在约零摄氏度和约百摄氏度之间的沉积温度，并且以不超过约一千科学立方厘米每分钟的速率引入四甲基硅烷的气流。 沉积压力保持在约1毫乇至约100乇之间，并且以不大于约2千瓦的功率产生射频等离子体放电。 当形成所需的碳化硅层厚度时，等离子体放电停止。

公开(公告)号：US08434394B1

公开(公告)日：2013-05-07

申请号：US12580412

申请日：2009-10-16

申请人： Gregory Malejko ,  Daniel Pascua ,  Peter Burke ,  Keith Fulton

发明人： Gregory Malejko ,  Daniel Pascua ,  Peter Burke ,  Keith Fulton

IPC分类号： F41F3/00 ,  F42B15/00

CPC分类号： F42B14/06 ,  F42B10/14 ,  F42B15/105 ,  F42B15/36

摘要： An apparatus for adapting a rocket-assisted artillery projectile of a first caliber for firing from a smooth bore tube of a second caliber may include an adapter for connecting to an aft end of the rocket-assisted artillery projectile. The adapter may include a main channel for receiving rocket exhaust, a plurality of sub-channels that lead from the main channel to an exterior of the adapter, and an ignition channel that leads from the main channel to an ignition delay disposed in the adapter. A tail boom may be fixed to an aft end of the adapter. The tail boom may include an opening in a fore end that communicates with the ignition delay in the adapter. Lifting surfaces, such as fins, may be attached to the tail boom.

摘要翻译： 用于使来自第二口径的光滑钻孔管的第一口径的火箭辅助炮弹的适配装置可以包括用于连接到火箭辅助炮弹的后端的适配器。 适配器可以包括用于接收火箭排气的主通道，从主通道引导到适配器的外部的多个子通道以及从主通道引导到设置在适配器中的点火延迟的点火通道。 尾杆可以固定到适配器的后端。 尾杆可以包括与适配器中的点火延迟相通的前端开口。 提升表面，例如翅片，可附接到尾部吊杆。

公开(公告)号：US20070272058A1

公开(公告)日：2007-11-29

申请号：US10576852

申请日：2004-10-16

申请人： Andreas Orth ,  David Leigh ,  Peter Burke

发明人： Andreas Orth ,  David Leigh ,  Peter Burke

IPC分类号： C21B15/00 ,  C22B3/02

CPC分类号： F27B3/18 ,  C21B5/023 ,  C21B13/00 ,  C21B13/0013 ,  C21B13/143 ,  C21C5/567 ,  F27D13/00 ,  Y02P10/216

摘要： The present invention relates to a direct smelting plant and a direct smelting process for producing molten metal from a metalliferous feed material, such as ores, partly reduced ores, and metal-containing waste streams, the latter of which comprising the steps of (a) pretreating metalliferous feed material in a pretreatment unit and producing pretreated feed material having a temperature of at least 200° C., (b) storing pretreated metalliferous feed material having a temperature of at least 200° C. under pressure in a hot feed material storage means, (c) transferring pretreated metalliferous feed material having a temperature of at least 200° C. under pressure in a hot feed material transfer line to a solids delivery means of a direct smelting vessel, and (d) delivering pretreated metalliferous feed material into the direct smelting vessel and smelting metalliferous feed material to molten metal in the vessel.

摘要翻译： 本发明涉及一种直接熔炼设备和用于从含金属的原料如矿石，部分还原的矿石和含金属的废物流中生产熔融金属的直接熔炼方法，后者包括以下步骤：（a） 在预处理单元中预处理含金属进料，并生产温度至少为200℃的预处理进料;（b）在热进料材料储存器中储存温度至少为200℃的预处理含金属进料 是指（c）在热进料输送管线中将压力为至少200℃的预处理的含金属进料传送到直接熔炼容器的固体输送装置，以及（d）将预处理的含金属进料输送到 直接熔炼容器和冶炼含金属进料到容器中的熔融金属。

公开(公告)号：US20070243326A1

公开(公告)日：2007-10-18

申请号：US11198902

申请日：2005-08-04

申请人： Peter Burke ,  Zhen Yu

发明人： Peter Burke ,  Zhen Yu

IPC分类号： C23C16/00 ,  D01F9/12

CPC分类号： D01F9/133 ,  B01J23/862 ,  B01J23/8993 ,  B01J37/0211 ,  B01J37/0215 ,  B01J37/024 ,  B82Y30/00 ,  B82Y40/00 ,  C01B32/162 ,  C01B2202/02 ,  C01B2202/34 ,  C01B2202/36 ,  D01F9/127 ,  Y10S427/102

摘要： Systems and methods for synthesizing ultra long carbon nanotubes comprising one or more metal underlayer platforms that allow the nanotube to grow freely suspended from the substrate. A modified gas-flow injector is used to reduce the gas flow turbulence during nanotube growth. Nanotube electrodes are formed by growing arrays of aligned nanotubes between two metal underlayer platforms.

摘要翻译： 用于合成超长碳纳米管的系统和方法，其包含一个或多个金属底层平台，其允许纳米管自由地悬浮在基底上。 改进的气流注入器用于减少纳米管生长期间的气流湍流。 纳米管电极通过在两个金属底层平台之间生长排列的纳米管阵列而形成。

公开(公告)号：US07179736B2

公开(公告)日：2007-02-20

申请号：US10966074

申请日：2004-10-14

申请人： Byung-Sung Leo Kwak ,  Peter Burke ,  Sey-Shing Sun

发明人： Byung-Sung Leo Kwak ,  Peter Burke ,  Sey-Shing Sun

IPC分类号： H01L21/4763

CPC分类号： H01L21/76877 ,  C25D5/18 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/7684

摘要： The present invention relates to a method of fabricating planar semiconductor wafers. The method comprises forming a dielectric layer on a semiconductor wafer surface, the semiconductor wafer surface having vias, trenches and planar regions. A barrier and seed metal layer is then formed on the dielectric layer. The wafer is next place in a plating bath that includes an accelerator, which tends to collect in the vias and trenches to accelerate the rate of plating in these areas relative to the planar regions of the wafer. After the gapfill point is reached, the plating is stopped by removing the plating bias on wafer. An equilibrium period is then introduced into the process, allowing higher concentrations of accelerator additives and other components of the bath)] above the via and trench regions to equilibrate in the plating bath. The bulk plating on the wafer is resumed after equilibration. Over-plating on the wafer in the areas of the vias and trenches is therefore avoided, resulting in a more planar metallization layer on the wafer, without the use of a leveler additive which adversely affects the gapfill capability.

摘要翻译： 本发明涉及一种制造平面半导体晶片的方法。 该方法包括在半导体晶片表面上形成电介质层，该半导体晶片表面具有通孔，沟槽和平面区域。 然后在电介质层上形成阻挡层和种子金属层。 晶片是包含加速器的镀液中的下一个位置，该加速器倾向于在通路和沟槽中收集，以加速相对于晶片的平面区域在这些区域中的电镀速率。 达到间隙填充点后，通过去除晶片上的电镀偏压来停止电镀。 然后在该过程中引入平衡时段，允许较高浓度的促进剂添加剂和浴中的其它组分）]在通孔和沟槽区域上方在电镀浴中平衡。 平衡后恢复晶片上的块体电镀。 因此避免了在通孔和沟槽区域上的晶片上的过电镀，导致晶片上更平面的金属化层，而不使用不利地影响间隙填充能力的矫直添加剂。