公开(公告)号：US20060237799A1

公开(公告)日：2006-10-26

申请号：US11112768

申请日：2005-04-21

申请人： Hongquiang Lu ,  Peter Burke ,  Wilbur Catabay

发明人： Hongquiang Lu ,  Peter Burke ,  Wilbur Catabay

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： G11C23/00 ,  B82Y10/00 ,  G11C13/025 ,  H01L51/0048 ,  H01L51/0052

摘要： The present invention is directed to structures and methods of fabricating nanotube electromechanical memory cells having a bottom electrode with a substantially planar contact surface. The bottom electrode is configured so that during the operation of the memory cell the nanotube crossbar of the cell can make contact with a substantially planar surface of the bottom electrode.

摘要翻译： 本发明涉及制造具有基本平坦的接触表面的底部电极的纳米管机电存储单元的结构和方法。 底部电极被配置为使得在存储器单元的操作期间，电池的纳米管横截面可以与底部电极的基本平坦的表面接触。

公开(公告)号：US20090256217A1

公开(公告)日：2009-10-15

申请号：US12102700

申请日：2008-04-14

申请人： Hongquiang Lu ,  Peter A. Burke ,  Wilbur Catabay

发明人： Hongquiang Lu ,  Peter A. Burke ,  Wilbur Catabay

IPC分类号： H01L27/00 ,  H01L21/02

CPC分类号： G11C13/025 ,  B82Y10/00 ,  G11C23/00 ,  G11C2213/16 ,  H01L21/76849 ,  H01L23/485 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention is directed to structures and methods of fabricating nanotube electromechanical memory cells having a bottom electrode with a substantially planar contact surface. The bottom electrode is configured so that during the operation of the memory cell the nanotube crossbar of the cell can make contact with a substantially planar surface of the bottom electrode.

摘要翻译： 本发明涉及制造具有基本平坦的接触表面的底部电极的纳米管机电存储单元的结构和方法。 底部电极被配置为使得在存储器单元的操作期间，电池的纳米管横截面可以与底部电极的基本平坦的表面接触。

公开(公告)号：US20070190784A1

公开(公告)日：2007-08-16

申请号：US11736402

申请日：2007-04-17

申请人： Hao Cui ,  Peter Burke ,  Wilbur Catabay

发明人： Hao Cui ,  Peter Burke ,  Wilbur Catabay

IPC分类号： H01L21/44

CPC分类号： H01L21/76832 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/76883

摘要： Embodiments of the invention include a copper interconnect structure having increased electromigration lifetime. Such structures can include a semiconductor substrate having a copper layer formed thereon. A dielectric barrier stack is formed on the copper layer. The dielectric barrier stack includes a first portion formed adjacent to the copper layer and a second portion formed on the first portion, the first portion having improved adhesion to copper relative to the second portion and both portions are formed having resistance to copper diffusion. The invention also includes several embodiments for constructing such structures. Adhesion of the dielectric barrier stack to copper can be increased by plasma treating or ion implanting selected portions of the dielectric barrier stack with adhesion enhancing materials to increase the concentration of such materials in the stack.

摘要翻译： 本发明的实施例包括具有增加的电迁移寿命的铜互连结构。 这种结构可以包括其上形成有铜层的半导体衬底。 在铜层上形成介电阻挡层叠体。 电介质势垒叠层包括邻近铜层形成的第一部分和形成在第一部分上的第二部分，第一部分具有相对于第二部分具有改进的铜的粘合性，并且两个部分形成为具有耐铜扩散性。 本发明还包括用于构造这种结构的几个实施例。 可以通过等离子体处理或离子注入电介质阻挡层的选定部分与粘合增强材料来增加电介质阻挡层与铜的附着，以增加堆叠中这种材料的浓度。

公开(公告)号：US20060035457A1

公开(公告)日：2006-02-16

申请号：US10915166

申请日：2004-08-10

申请人： Richard Carter ,  Peter Burke ,  Wilbur Catabay ,  Zhihai Wang ,  Wei-Jen Hsia

发明人： Richard Carter ,  Peter Burke ,  Wilbur Catabay ,  Zhihai Wang ,  Wei-Jen Hsia

IPC分类号： H01L21/4763

CPC分类号： H01L21/76885 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76837

摘要： An improvement to a method of fabricating an integrated circuit. All dielectric material that is laterally surrounding an electrically conductive interconnect is removed, while leaving the dielectric material that directly underlies the electrically conductive interconnect. The electrically conductive interconnect is back filled with a low k material, where the low k material provides low capacitance between laterally adjacent electrically conductive interconnects, and the remaining dielectric material underlying the electrically conductive interconnects provides structural support to the electrically conductive interconnects.

摘要翻译： 对集成电路的制造方法的改进。 移除横向围绕导电互连的所有电介质材料，同时留下直接位于导电互连之下的电介质材料。 导电互连件用低k材料填充，其中低k材料在横向相邻的导电互连之间提供低电容，并且导电互连件下面的剩余电介质材料为导电互连提供结构支撑。

公开(公告)号：US20050090036A1

公开(公告)日：2005-04-28

申请号：US10691400

申请日：2003-10-22

申请人： Hao Cui ,  Peter Burke ,  Wilbur Catabay

发明人： Hao Cui ,  Peter Burke ,  Wilbur Catabay

IPC分类号： C23C16/32 ,  H01L21/00 ,  H01L21/314 ,  H01L21/46 ,  H01L21/768 ,  H01L29/15

CPC分类号： H01L21/02167 ,  C23C16/325 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/3148 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76826 ,  H01L21/76828

摘要： A method for forming a substantially oxygen-free silicon carbide layer on a substrate, where the silicon carbide layer has a dielectric constant of less than about four. The substrate is held at a deposition temperature of between about zero centigrade and about one hundred centigrade, and a gas flow of tetramethylsilane is introduced at a rate of no more than about one thousand scientific cubic centimeters per minute. The deposition pressure is held between about one milli Torr and about one hundred Torr, and a radio frequency plasma discharge is produced with a power of no more than about two kilowatts. The plasma discharge is halted when a desired thickness of the silicon carbide layer has been formed.

摘要翻译： 在基底上形成基本上无氧的碳化硅层的方法，其中碳化硅层的介电常数小于约4。 基板保持在约零摄氏度和约百摄氏度之间的沉积温度，并且以不超过约一千科学立方厘米每分钟的速率引入四甲基硅烷的气流。 沉积压力保持在约1毫乇至约100乇之间，并且以不大于约2千瓦的功率产生射频等离子体放电。 当形成所需的碳化硅层厚度时，等离子体放电停止。

公开(公告)号：US20050208758A1

公开(公告)日：2005-09-22

申请号：US11131003

申请日：2005-05-16

申请人： Hong-Qiang Lu ,  Peter Burke ,  Wilbur Catabay

发明人： Hong-Qiang Lu ,  Peter Burke ,  Wilbur Catabay

IPC分类号： H01L21/312 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L21/02211 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/02315 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/3121 ,  H01L21/76807 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76832 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention is directed to improved dielectric copper barrier layer and related interconnect structures. One structure includes a semiconductor substrate having a copper line. An insulating layer formed of at least one of silicon and carbon is formed on the underlying copper line. An opening is formed in the insulating layer to expose a portion of the copper line. The inner surface of the opening in the insulating layer has a dielectric barrier layer formed thereon to prevent the diffusion of copper into the insulating layer. A copper plug is formed to fill the opening and make electrical contact with the underlying copper interconnect structure. Aspects of the invention also include methods for forming the dielectric copper barrier layers and associate copper interconnects to the underlying copper lines.

摘要翻译： 本发明涉及改进的介电铜阻挡层和相关互连结构。 一种结构包括具有铜线的半导体衬底。 在下面的铜线上形成由硅和碳中的至少一种形成的绝缘层。 在绝缘层中形成开口以露出铜线的一部分。 绝缘层中的开口的内表面具有形成在其上的电介质阻挡层，以防止铜扩散到绝缘层中。 形成铜塞以填充开口并与下面的铜互连结构电接触。 本发明的方面还包括用于形成电介质铜阻挡层和将铜互连连接到下面的铜线的方法。

公开(公告)号：US20050176216A1

公开(公告)日：2005-08-11

申请号：US11106307

申请日：2005-04-14

申请人： Hao Cui ,  Peter Burke ,  Wilbur Catabay

发明人： Hao Cui ,  Peter Burke ,  Wilbur Catabay

IPC分类号： C23C16/32 ,  H01L21/00 ,  H01L21/314 ,  H01L21/46 ,  H01L21/768 ,  H01L29/15

CPC分类号： H01L21/02167 ,  C23C16/325 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/3148 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76826 ,  H01L21/76828

摘要： A method for forming a substantially oxygen-free silicon carbide layer on a substrate, where the silicon carbide layer has a dielectric constant of less than about four. The substrate is held at a deposition temperature of between about zero centigrade and about one hundred centigrade, and a gas flow of tetramethylsilane is introduced at a rate of no more than about one thousand scientific cubic centimeters per minute. The deposition pressure is held between about one milli Torr and about one hundred Torr, and a radio frequency plasma discharge is produced with a power of no more than about two kilowatts. The plasma discharge is halted when a desired thickness of the silicon carbide layer has been formed.

公开(公告)号：US20060118523A1

公开(公告)日：2006-06-08

申请号：US11337460

申请日：2006-01-23

申请人： Wilbur Catabay ,  Wei-Jen Hsia ,  Hao Cui

发明人： Wilbur Catabay ,  Wei-Jen Hsia ,  Hao Cui

IPC分类号： B44C1/22 ,  C23F1/00 ,  C03C15/00

CPC分类号： B23H5/08 ,  C23F1/02 ,  C23F4/00 ,  C25F3/02 ,  H01L21/02063 ,  H01L21/32115 ,  H01L21/3212 ,  H01L21/32136 ,  H01L21/7684

摘要： A method of forming a planarized layer on a substrate, where the substrate is cleaned, and the layer is formed having a surface with high portions and low portions. A resistive mask is formed over the low portions of the layer, but not over the high portions of the layer. The surface of the layer is etched, where the high portions of the layer are exposed to the etch, but the low portions of the layer underlying the resistive mask are not exposed to the etch. The etch of the surface of the layer is continued until the high portions of the layer are at substantially the same level as the low portions of the layer, thereby providing an initial planarization of the surface of the layer. The resistive mask is removed from the surface of the layer, and all of the surface of the layer is planarized to provide a planarized layer.

摘要翻译： 在衬底上形成平坦化层的方法，其中衬底被清洁，并且形成具有高部分和低部分的表面的层。 电阻掩模形成在层的低部分上，但不在层的高部分之上。 蚀刻层的表面，其中层的高部分暴露于蚀刻，但是电阻掩模下面的层的低部分不暴露于蚀刻。 层的表面的蚀刻继续进行直到层的高部分与层的低部分基本相同的水平，从而提供层的表面的初始平坦化。 电阻掩模从层的表面去除，并且层的所有表面被平坦化以提供平坦化层。

公开(公告)号：US20080308937A1

公开(公告)日：2008-12-18

申请号：US12138595

申请日：2008-06-13

申请人： Wilbur Catabay ,  Julian Searle ,  Wei-Jen Hsia ,  Milan Prejda ,  Rohini Ranganathan ,  Lahcene Smati ,  Majid Milani

发明人： Wilbur Catabay ,  Julian Searle ,  Wei-Jen Hsia ,  Milan Prejda ,  Rohini Ranganathan ,  Lahcene Smati ,  Majid Milani

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L23/53295 ,  H01L23/53223 ,  H01L23/53266 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of copper-free semiconductor device interfaces and methods for forming and/or utilizing the same are provided herein. In some embodiments, a semiconductor structure may include a substrate having an exposed copper-containing feature; and a copper-free interface disposed over the substrate and providing a conductive interconnect between the copper-containing feature and an upper surface of the copper-free interface to facilitate electrical coupling of the substrate to a semiconductor device while physically isolating the semiconductor device from the copper-containing feature.

摘要翻译： 本文提供了无铜半导体器件界面的实施例以及用于形成和/或利用其的方法。 在一些实施例中，半导体结构可以包括具有暴露的含铜特征的衬底; 以及设置在衬底上方的无铜界面，并且在含铜特征和无铜界面的上表面之间提供导电互连，以便于将衬底电耦合到半导体器件，同时将半导体器件与 含铜功能。

公开(公告)号：US20070178692A1

公开(公告)日：2007-08-02

申请号：US11733673

申请日：2007-04-10

申请人： Wilbur Catabay ,  Zhihai Wang ,  Ping Li

发明人： Wilbur Catabay ,  Zhihai Wang ,  Ping Li

IPC分类号： H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/2855 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76858 ,  H01L21/76859 ,  H01L21/76864 ,  H01L21/76871 ,  H01L21/76873 ,  H01L21/76874 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the invention include a method for forming a copper interconnect having a bi-layer copper barrier layer. The method comprises the steps of providing a substrate in a processing chamber, the substrate having a low-K dielectric insulating layer and an opening in the insulating layer. A first barrier layer of tantalum/tantalum nitride is formed on the insulating layer and in the opening. A second barrier layer is formed on the first barrier layer. The second barrier layer consisting of a material selected from the group of palladium, chromium, tantalum, magnesium, and molybdenum. A copper seed layer is formed on the second barrier layer and a bulk copper layer is formed on the seed layer. The substrate is annealed and subject to further processing which can include planarization. Other embodiments include providing a substrate in a processing chamber and forming a copper seed layer on the substrate. The seed layer is implanted with barrier materials to form an implanted seed layer followed by bulk copper-containing layer formation. The substrate is annealed to form a final barrier layer. In a related embodiment the step of forming a seed layer is replaced with the steps of forming a first barrier layer on the substrate and forming a copper seed layer on the first barrier layer. After implantation of barrier material into the seed layer and bulk deposition of copper-containing material, the substrate is annealed to form a final barrier layer. In yet another related embodiment the step of forming a seed layer is replaced with the steps of forming a first barrier layer on the substrate and forming a second barrier layer on the first layer. A copper seed layer is formed on the second barrier layer. After implantation of barrier material into the seed layer and bulk deposition of copper-containing material, the substrate is annealed to form a final barrier layer.

摘要翻译： 本发明的实施例包括一种形成具有双层铜阻挡层的铜互连的方法。 该方法包括以下步骤：在处理室中提供衬底，所述衬底具有低K电介质绝缘层和绝缘层中的开口。 在绝缘层和开口中形成钽/氮化钽的第一阻挡层。 在第一阻挡层上形成第二阻挡层。 第二阻挡层由选自钯，铬，钽，镁和钼的材料组成。 在第二阻挡层上形成铜籽晶层，在籽晶层上形成体铜层。 将衬底退火并进行可包括平坦化的进一步加工。 其他实施例包括在处理室中提供衬底并在衬底上形成铜籽晶层。 种子层被植入阻挡材料以形成植入的种子层，然后形成大块含铜层。 将衬底退火以形成最终的阻挡层。 在相关实施例中，形成种子层的步骤被替换为在衬底上形成第一阻挡层并在第一阻挡层上形成铜籽晶层的步骤。 在将阻挡材料植入种子层和含铜材料的大量沉积之后，将衬底退火以形成最终的阻挡层。 在另一相关实施例中，形成种子层的步骤被替换为在衬底上形成第一阻挡层并在第一层上形成第二阻挡层的步骤。 在第二阻挡层上形成铜籽晶层。 在将阻挡材料植入种子层和含铜材料的大量沉积之后，将衬底退火以形成最终的阻挡层。