摘要:
Thermal isolation mesas 36 comprising a porous material 64 are used to thermally insulate sensing integrated circuitry 44 from pixels 34 of an uncooled IR detector hybrid system 30. The porous material 64 is preferably a silicon-dioxide xerogel. The mesas 36 may also comprise a protective film 66.
摘要:
This is a device and method of forming such, wherein the device has an amorphous "TEFLON" (TFE AF) layer. The method comprising: depositing an TFE AF layer 36 on a substrate; combining a fluorosurfactant with a first material to produce a second material 38; and depositing the second material 38 on the TFE AF layer 36. The method may include: patterning and etching the second material; removing the second material; and forming a third material 42 on the TFE AF layer 44. The third material may be a metal or a semiconductor. The ZFSNF fluorosurfactant may be combined with a photoresist and then patterned and etched. The TFE AF layer may also be heated. A second coating of the second material may also be added.
摘要:
Thermal isolation mesas 36 comprising a porous material 64 are used to thermally insulate sensing integrated circuitry 44 from pixels 34 of an uncooled IR detector hybrid system 30. The porous material 64 is preferably a silicon-dioxide xerogel. The mesas 36 may also comprise a protective film 66.
摘要:
An optical coating for an uncooled focal plane array detector where the optical coating comprises a porous film. The porous film preferably comprises a xerogel.
摘要:
A porous film 64 is used to thermally insulate sensing integrated circuitry 44 from pixels 34 of an uncooled IR detector hybrid system 30. The porous film 64 is preferably a silicon-dioxide xerogel. A protective film 65 may be deposited on the porous film 64.
摘要:
A porous film 64 is used to thermally insulate sensing integrated circuitry 44 from pixels 34 of an uncooled IR detector hybrid system 30. The porous film 64 is preferably a silicon-dioxide xerogel. A protective film 65 may be deposited on the porous film 64.
摘要:
A thermal detector having an optical coating comprising a porous film 64. The porous film preferably comprises a xerogel or aerogel and is greater than 80% porous. An optional optical impedance matching layer 66 may be deposited over the porous film 64. Advantages include decreased thickness of the thermal sensor, improved acuity of the image produced by the system, lower manufacturing temperatures, and the ability to use electrodes that are opaque to infrared energy.
摘要:
An operating method for a non-volatile memory device is applicable on a non-volatile memory device in which a substrate is disposed. The substrate includes a trench, a first conductive type first well region disposed in the substrate, and a second conductive type second well region disposed above the first conductive type first well region. The operating method includes applying a first voltage to a control gate, a second voltage to a drain region, and a third voltage to a source region. Besides, a channel F-N tunneling effect is employed to program a memory cell.
摘要:
A non-volatile memory is provided. A substrate has at least two isolation structures therein to define an active area. A well is located in the substrate. A shallow doped region is located in the well. At least two stacked gate structures are located on the substrate. Pocket doped regions are located in the substrate at the peripheries of the stacked gate structures; each of the pocket doped regions extends under the stacked gate structure. Drain regions are located in the pocket doped regions at the peripheries of the stacked gate structures. An auxiliary gate layer is located on the substrate between the stacked gate structures. A gate dielectric layer is located between the auxiliary gate layer and the substrate and between the auxiliary gate layer and the stacked gate structure. Plugs are located on the substrate and extended to connect with the pocket doped region and the drain regions therein.
摘要:
A non-volatile memory having a plurality of gate structures, a plurality of charge storage layers and two doped regions is provided. The gate structures are disposed on the substrate and connected in series. The charge storage layers are disposed between every two neighboring gate structures respectively. The gate structures and the charge storage layers form a memory cell column. The two doped regions are disposed in the substrate at both sides of the memory cell column.