公开(公告)号：US20110213922A1

公开(公告)日：2011-09-01

申请号：US13108143

申请日：2011-05-16

Applicant: Hye-jin KIM ,  Kwang-jin LEE ,  Du-eung KIM

Inventor： Hye-jin KIM ,  Kwang-jin LEE ,  Du-eung KIM

IPC: G06F12/02

CPC classification number: G11C13/0064 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0092

Abstract: A method of operating a phase change random access memory (PRAM) device includes performing a program operation to store data in selected PRAM cells of the device, wherein the program operation comprises a plurality of sequential program loops. The method further comprises suspending the program operation in the middle of the program operation, and after suspending the program operation, resuming the program operation in response to a resume command.

Abstract translation: 操作相变随机存取存储器（PRAM）装置的方法包括执行程序操作以将数据存储在所述装置的所选PRAM单元中，其中所述程序操作包括多个顺序程序循环。 该方法还包括在编程操作的中间暂停编程操作，并且在暂停编程操作之后，响应于恢复命令恢复程序操作。

公开(公告)号：US20130026656A1

公开(公告)日：2013-01-31

申请号：US13630619

申请日：2012-09-28

Applicant: Hye-jin KIM ,  Byung-seo KIM ,  Sun-il YOUN

Inventor： Hye-jin KIM ,  Byung-seo KIM ,  Sun-il YOUN

IPC: H01L23/48

CPC classification number: H01L25/0657 ,  H01L24/48 ,  H01L24/49 ,  H01L25/18 ,  H01L2224/05553 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/4911 ,  H01L2225/06506 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A plurality of semiconductor chips may be stacked on the substrate, and each of them may include at least one electrode pad. At least one of the plurality of semiconductor chips may include at least one redistribution pad configured to electrically connect with the at least one electrode pad.

公开(公告)号：US20090102037A1

公开(公告)日：2009-04-23

申请号：US12251534

申请日：2008-10-15

Applicant: Hye-jin KIM

Inventor： Hye-jin KIM

IPC: H01L23/488 ,  H01L21/56

CPC classification number: H01L23/49816 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/05001 ,  H01L2224/05568 ,  H01L2224/05644 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01327 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/3436 ,  H05K2201/09572 ,  H05K2201/10666 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2224/05099 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package structure having a solder ball coupled to a chip pad and a manufacturing method thereof, a semiconductor package module, and a system. A circuit board includes a through hole therein, and a conductor is formed on a sidewall of the through hole. A first semiconductor chip including a first chip pad is mounted on the circuit board. A solder ball is disposed in the through hole and is bonded to the conductor and the first chip pad. Therefore, an underfill can be removed from a semiconductor package, and thus, the semiconductor package can be reduced in thickness.

Abstract translation: 一种具有耦合到芯片焊盘的焊球的半导体封装结构及其制造方法，半导体封装模块和系统。 电路板在其中包括通孔，并且导体形成在通孔的侧壁上。 包括第一芯片焊盘的第一半导体芯片安装在电路板上。 焊球设置在通孔中并且接合到导体和第一芯片焊盘。 因此，可以从半导体封装中去除底部填充物，因此可以减小半导体封装的厚度。

公开(公告)号：US20080068897A1

公开(公告)日：2008-03-20

申请号：US11850128

申请日：2007-09-05

Applicant: Kwang-jin LEE ,  Woo-yeong CHO ,  Hye-jin KIM

Inventor： Kwang-jin LEE ,  Woo-yeong CHO ,  Hye-jin KIM

IPC: G11C7/10

CPC classification number: G11C7/1045 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/109 ,  G11C7/22

Abstract: A semiconductor memory device comprises a memory cell array comprising memory cells of a first type. The memory cell array performs write and read operations in response to signals designed for the operation of a memory cell array comprising memory cells of a type other than the first type.

Abstract translation: 半导体存储器件包括包括第一类型存储单元的存储单元阵列。 存储单元阵列响应于设计用于包括除了第一类型之外的类型的存储器单元的存储单元阵列的操作的信号执行写入和读取操作。

公开(公告)号：US20080055971A1

公开(公告)日：2008-03-06

申请号：US11834845

申请日：2007-08-07

Applicant: Hye-jin KIM ,  Kwang-jin LEE ,  Du-eung KIM

Inventor： Hye-jin KIM ,  Kwang-jin LEE ,  Du-eung KIM

IPC: G11C11/00

CPC classification number: G11C13/0064 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0092

Abstract: A method of operating a phase change random access memory (PRAM) device comprises performing a program operation to store data in selected PRAM cells of the device, wherein the program operation comprises a plurality of sequential program loops. The method further comprises suspending the program operation in the middle of the program operation, and after suspending the program operation, resuming the program operation in response to a resume command.

Abstract translation: 一种操作相变随机存取存储器（PRAM）装置的方法包括执行程序操作以将数据存储在所述装置的所选择的PRAM单元中，其中所述程序操作包括多个顺序程序循环。 该方法还包括在编程操作的中间暂停编程操作，并且在暂停编程操作之后，响应于恢复命令恢复程序操作。

公开(公告)号：US20130039124A1

公开(公告)日：2013-02-14

申请号：US13655666

申请日：2012-10-19

Applicant: Hye-jin KIM ,  Kwang-jin LEE ,  Du-eung KIM

Inventor： Hye-jin KIM ,  Kwang-jin LEE ,  Du-eung KIM

IPC: G11C11/00

CPC classification number: G11C13/0064 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0092

Abstract: A method of operating a phase change random access memory (PRAM) device includes performing a program operation to store data in selected PRAM cells of the device, wherein the program operation comprises a plurality of sequential program loops. The method further comprises suspending the program operation in the middle of the program operation, and after suspending the program operation, resuming the program operation in response to a resume command.

Abstract translation: 操作相变随机存取存储器（PRAM）装置的方法包括执行程序操作以将数据存储在所述装置的所选PRAM单元中，其中所述程序操作包括多个顺序程序循环。 该方法还包括在编程操作的中间暂停编程操作，并且在暂停编程操作之后，响应于恢复命令恢复程序操作。

公开(公告)号：US20100220521A1

公开(公告)日：2010-09-02

申请号：US12724679

申请日：2010-03-16

Applicant: Hye-jin KIM ,  Kwang-jin LEE ,  Du-eung KIM

Inventor： Hye-jin KIM ,  Kwang-jin LEE ,  Du-eung KIM

IPC: G11C11/00 ,  G11C7/00

CPC classification number: G11C13/0064 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0092

Abstract: A method of operating a phase change random access memory (PRAM) device comprises performing a program operation to store data in selected PRAM cells of the device, wherein the program operation comprises a plurality of sequential program loops. The method further comprises suspending the program operation in the middle of the program operation, and after suspending the program operation, resuming the program operation in response to a resume command.

Abstract translation: 一种操作相变随机存取存储器（PRAM）装置的方法包括执行程序操作以将数据存储在所述装置的所选择的PRAM单元中，其中所述程序操作包括多个顺序程序循环。 该方法还包括在编程操作的中间暂停编程操作，并且在暂停编程操作之后，响应于恢复命令恢复程序操作。

公开(公告)号：US20090129144A1

公开(公告)日：2009-05-21

申请号：US12256564

申请日：2008-10-23

Applicant: Hye-jin KIM ,  Sang-ki HWANG

Inventor： Hye-jin KIM ,  Sang-ki HWANG

IPC: G11C11/00 ,  G11C8/08 ,  G11C7/00

CPC classification number: G11C7/12 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C2213/72 ,  G11C2213/79

Abstract: Disclosed are a phase change memory device in which an active time is reduced and a method of discharging a bitline in the phase change memory device. In the phase change memory device having the reduced active time and the method of discharging the bitline in the phase change memory device, the bitline is either always discharged when the phase change memory device is in standby, is discharged after the active operation of the phase change memory device, or is discharged prior to and after the active operation of the phase change memory device.

Abstract translation: 公开了其中有效时间减少的相变存储器件以及在相变存储器件中放电位线的方法。 在相变存储器件中具有减小的有效时间的相变存储器件和放电位线的方法中，当相变存储器件处于待机状态时，位线或者总是被放电，在相位的有效操作之后被放电 更换存储器件，或在相变存储器件的有效操作之前和之后被放电。

公开(公告)号：US20080106930A1

公开(公告)日：2008-05-08

申请号：US11933536

申请日：2007-11-01

Applicant: Hye-jin KIM ,  Kwang-jin LEE ,  Du-eung KIM ,  Woo-yeong CHO ,  Chang-han CHOI ,  Ki-won LIM

Inventor： Hye-jin KIM ,  Kwang-jin LEE ,  Du-eung KIM ,  Woo-yeong CHO ,  Chang-han CHOI ,  Ki-won LIM

IPC: G11C11/00 ,  G11C7/00

CPC classification number: G11C8/06 ,  G11C8/10 ,  G11C13/0004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C29/12005 ,  G11C29/50 ,  G11C2013/0083 ,  G11C2013/0092

Abstract: A PRAM includes a memory cell array of phase change memory cells, and a write circuit receiving an externally provided first voltage and supplying a write pulse for writing data to the memory cells in a normal operation mode. The write circuit also receives an externally provided second voltage higher than the first voltage and supplies a firing pulse to at least one firing-failed phase change memory cell.

Abstract translation: PRAM包括相变存储单元的存储单元阵列和接收外部提供的第一电压的写入电路，并且在正常操作模式中提供用于将数据写入存储单元的写入脉冲。 写入电路还接收高于第一电压的外部提供的第二电压，并且向至少一个点火故障相变存储单元提供点火脉冲。