公开(公告)号：US07592709B2

公开(公告)日：2009-09-22

申请号：US11430900

申请日：2006-05-10

申请人： Hyun-soo Chung ,  Dong-hyeon Jang ,  Dong-ho Lee ,  In-young Lee

发明人： Hyun-soo Chung ,  Dong-hyeon Jang ,  Dong-ho Lee ,  In-young Lee

IPC分类号： H01L23/48 ,  H01L29/40 ,  H01L23/28

CPC分类号： H01L23/3128 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/06136 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/92147 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19103 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

摘要： A ball grid array type board on chip package may include an integrated circuit chip having an active surface that supports a plurality of contact pads. An interposer may be adhered to the active surface of the integrated circuit chip. At least one hole may be provided through the interposer to expose the contact pads. A board, which may have a first surface supporting a plurality of metal lines, may have a second surface adhered to the interposer. The board may have an opening through which the contact pads may be exposed. A plurality of bonding wires may connect the contact pads to the metal lines through the opening.

摘要翻译： 球栅阵列型片上芯片封装可以包括具有支撑多个接触焊盘的有源表面的集成电路芯片。 插入器可以粘附到集成电路芯片的有源表面。 可以通过插入件提供至少一个孔以暴露接触垫。 可以具有支撑多个金属线的第一表面的板可以具有粘附到插入件的第二表面。 板可以具有开口，接触垫可以穿过该开口露出。 多个接合线可以通过开口将接触垫连接到金属线。

公开(公告)号：US07923296B2

公开(公告)日：2011-04-12

申请号：US12385946

申请日：2009-04-24

申请人： Hyun-soo Chung ,  Dong-hyeon Jang ,  Dong-ho Lee ,  In-young Lee

发明人： Hyun-soo Chung ,  Dong-hyeon Jang ,  Dong-ho Lee ,  In-young Lee

IPC分类号： H01L21/00

CPC分类号： H01L23/3128 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/06136 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/92147 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19103 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

摘要： A ball grid array type board on chip package may include an integrated circuit chip having an active surface that supports a plurality of contact pads. An interposer may be adhered to the active surface of the integrated circuit chip. At least one hole may be provided through the interposer to expose the contact pads. A board, which may have a first surface supporting a plurality of metal lines, may have a second surface adhered to the interposer. The board may have an opening through which the contact pads may be exposed. A plurality of bonding wires may connect the contact pads to the metal lines through the opening.

摘要翻译： 球栅阵列型片上芯片封装可以包括具有支撑多个接触焊盘的有源表面的集成电路芯片。 插入器可以粘附到集成电路芯片的有源表面。 可以通过插入件提供至少一个孔以暴露接触垫。 可以具有支撑多个金属线的第一表面的板可以具有粘附到插入件的第二表面。 板可以具有开口，接触垫可以穿过该开口露出。 多个接合线可以通过开口将接触垫连接到金属线。

公开(公告)号：US20070096341A1

公开(公告)日：2007-05-03

申请号：US11430900

申请日：2006-05-10

申请人： Hyun-soo Chung ,  Dong-hyeon Jang ,  Dong-ho Lee ,  In-young Lee

发明人： Hyun-soo Chung ,  Dong-hyeon Jang ,  Dong-ho Lee ,  In-young Lee

IPC分类号： H01L23/52

CPC分类号： H01L23/3128 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/06136 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/92147 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19103 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

摘要： A ball grid array type board on chip package may include an integrated circuit chip having an active surface that supports a plurality of contact pads. An interposer may be adhered to the active surface of the integrated circuit chip. At least one hole may be provided through the interposer to expose the contact pads. A board, which may have a first surface supporting a plurality of metal lines, may have a second surface adhered to the interposer. The board may have an opening through which the contact pads may be exposed. A plurality of bonding wires may connect the contact pads to the metal lines through the opening.

摘要翻译： 球栅阵列型片上芯片封装可以包括具有支撑多个接触焊盘的有源表面的集成电路芯片。 插入器可以粘附到集成电路芯片的有源表面。 可以通过插入件提供至少一个孔以暴露接触垫。 可以具有支撑多个金属线的第一表面的板可以具有粘附到插入件的第二表面。 板可以具有开口，接触垫可以穿过该开口露出。 多个接合线可以通过开口将接触垫连接到金属线。

公开(公告)号：US20090215229A1

公开(公告)日：2009-08-27

申请号：US12385946

申请日：2009-04-24

申请人： Hyun-soo Chung ,  Dong-hyeon Jang ,  Dong-ho Lee ,  In-young Lee

发明人： Hyun-soo Chung ,  Dong-hyeon Jang ,  Dong-ho Lee ,  In-young Lee

IPC分类号： H01L21/50

CPC分类号： H01L23/3128 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/06136 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/92147 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19103 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

摘要： A ball grid array type board on chip package may include an integrated circuit chip having an active surface that supports a plurality of contact pads. An interposer may be adhered to the active surface of the integrated circuit chip. At least one hole may be provided through the interposer to expose the contact pads. A board, which may have a first surface supporting a plurality of metal lines, may have a second surface adhered to the interposer. The board may have an opening through which the contact pads may be exposed. A plurality of bonding wires may connect the contact pads to the metal lines through the opening.

公开(公告)号：US07851256B2

公开(公告)日：2010-12-14

申请号：US12285923

申请日：2008-10-16

申请人： Hyun-soo Chung ,  Dong-ho Lee ,  Seong-deok Hwang ,  Sun-won Kang ,  Seung-duk Baek

发明人： Hyun-soo Chung ,  Dong-ho Lee ,  Seong-deok Hwang ,  Sun-won Kang ,  Seung-duk Baek

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L25/0657 ,  H01L24/02 ,  H01L24/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/16112 ,  H01L2224/16147 ,  H01L2224/16237 ,  H01L2224/2518 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2224/81365 ,  H01L2224/81385 ,  H01L2224/81805 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/014

摘要： Provided is a method of fabricating a chip-on-chip (COC) semiconductor device. The method of fabricating a chip-on-chip (COC) semiconductor device may include preparing a first semiconductor device with a metal wiring having at least one discontinuous spot formed therein, preparing a second semiconductor device with at least one bump formed on a surface of the second semiconductor device corresponding to the at least one discontinuous spot, aligning the first semiconductor device onto the second semiconductor device, and connecting the at least one bump of the second semiconductor device to the at least one discontinuous spot formed in the metal wiring of the first semiconductor device.

摘要翻译： 提供了一种制造片上芯片（COC）半导体器件的方法。 片上芯片（COC）半导体器件的制造方法可以包括：准备具有在其中形成有至少一个不连续点的金属布线的第一半导体器件，制备第二半导体器件，其中至少一个凸点形成在 所述第二半导体器件对应于所述至少一个不连续点，将所述第一半导体器件对准到所述第二半导体器件上，并且将所述第二半导体器件的所述至少一个突起连接到形成在所述第二半导体器件的所述金属布线中的所述至少一个不连续点 第一半导体器件。

公开(公告)号：US20070176240A1

公开(公告)日：2007-08-02

申请号：US11556931

申请日：2006-11-06

申请人： Hyun-soo Chung ,  Seung-duk Baek ,  Ju-il Choi ,  Dong-ho Lee

发明人： Hyun-soo Chung ,  Seung-duk Baek ,  Ju-il Choi ,  Dong-ho Lee

IPC分类号： H01L23/62

CPC分类号： H01L24/11 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/12 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02321 ,  H01L2224/02335 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/451 ,  H01L2224/4813 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00014

摘要： A method of forming a wire structure connecting to a bonding pad of a semiconductor chip includes depositing a passivation layer on an active surface of the semiconductor chip, depositing a seed metal layer on the bonding pad and the passivation layer, depositing a metal layer on the seed metal layer, etching selected portions of the seed metal layer, leaving unetched a first area, overlapping the bonding pad and a second area overlapping a connection pad, wherein the wire structure is formed by the metal layer being electrically connected to the bonding pad and the connection pad, but floating from the passivation layer, and depositing an insulting layer on the wire structure.

摘要翻译： 形成连接到半导体芯片的焊盘的导线结构的方法包括在半导体芯片的有源表面上沉积钝化层，在焊盘和钝化层上沉积种子金属层，在金属层上沉积金属层 种子金属层，蚀刻种子金属层的选定部分，留下未蚀刻的第一区域，与接合焊盘重叠，第二区域与连接焊盘重叠，其中线结构由金属层电连接到接合焊盘， 连接焊盘，但是从钝化层浮起，并且在导线结构上沉积绝缘层。

公开(公告)号：US07767576B2

公开(公告)日：2010-08-03

申请号：US11556931

申请日：2006-11-06

申请人： Hyun-soo Chung ,  Seung-duk Baek ,  Ju-il Choi ,  Dong-ho Lee

发明人： Hyun-soo Chung ,  Seung-duk Baek ,  Ju-il Choi ,  Dong-ho Lee

IPC分类号： H01L21/4763

CPC分类号： H01L24/11 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/12 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02321 ,  H01L2224/02335 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/451 ,  H01L2224/4813 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00014

摘要： A method of forming a wire structure connecting to a bonding pad of a semiconductor chip includes depositing a passivation layer on an active surface of the semiconductor chip, depositing a seed metal layer on the bonding pad and the passivation layer, depositing a metal layer on the seed metal layer, etching selected portions of the seed metal layer, leaving unetched a first area, overlapping the bonding pad and a second area overlapping a connection pad, wherein the wire structure is formed by the metal layer being electrically connected to the bonding pad and the connection pad, but floating from the passivation layer, and depositing an insulting layer on the wire structure.

摘要翻译： 形成连接到半导体芯片的焊盘的导线结构的方法包括在半导体芯片的有源表面上沉积钝化层，在焊盘和钝化层上沉积种子金属层，在金属层上沉积金属层 种子金属层，蚀刻种子金属层的选定部分，留下未蚀刻的第一区域，与接合焊盘重叠，第二区域与连接焊盘重叠，其中线结构由金属层电连接到接合焊盘， 连接焊盘，但是从钝化层浮起，并且在导线结构上沉积绝缘层。

公开(公告)号：US20090111217A1

公开(公告)日：2009-04-30

申请号：US12285923

申请日：2008-10-16

申请人： Hyun-soo Chung ,  Dong-ho Lee ,  Seong-deok Hwang ,  Sun-won Kang ,  Seung-duk Baek

发明人： Hyun-soo Chung ,  Dong-ho Lee ,  Seong-deok Hwang ,  Sun-won Kang ,  Seung-duk Baek

IPC分类号： H01L21/00

CPC分类号： H01L25/0657 ,  H01L24/02 ,  H01L24/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/16112 ,  H01L2224/16147 ,  H01L2224/16237 ,  H01L2224/2518 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2224/81365 ,  H01L2224/81385 ,  H01L2224/81805 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/014

摘要： Provided is a method of fabricating a chip-on-chip (COC) semiconductor device. The method of fabricating a chip-on-chip (COC) semiconductor device may include preparing a first semiconductor device with a metal wiring having at least one discontinuous spot formed therein, preparing a second semiconductor device with at least one bump formed on a surface of the second semiconductor device corresponding to the at least one discontinuous spot, aligning the first semiconductor device onto the second semiconductor device, and connecting the at least one bump of the second semiconductor device to the at least one discontinuous spot formed in the metal wiring of the first semiconductor device.

摘要翻译： 提供了一种制造片上芯片（COC）半导体器件的方法。 片上芯片（COC）半导体器件的制造方法可以包括：准备具有在其中形成有至少一个不连续点的金属布线的第一半导体器件，制备第二半导体器件，其中至少一个凸块形成在 所述第二半导体器件对应于所述至少一个不连续点，将所述第一半导体器件对准到所述第二半导体器件上，并且将所述第二半导体器件的所述至少一个突起连接到形成在所述第二半导体器件的所述金属布线中的所述至少一个不连续点 第一半导体器件。

公开(公告)号：US09382575B2

公开(公告)日：2016-07-05

申请号：US13614881

申请日：2012-09-13

申请人： Kun-sun Eom ,  Dong-ho Lee ,  Jeo-young Shim ,  Hee-jeong Jeong ,  Tae-han Jeon

发明人： Kun-sun Eom ,  Dong-ho Lee ,  Jeo-young Shim ,  Hee-jeong Jeong ,  Tae-han Jeon

IPC分类号： C12Q1/68 ,  G01N33/487

CPC分类号： C12Q1/68 ,  G01N33/48721 ,  C12Q2565/631

摘要： A biomolecule detection apparatus comprising a nanopore device having a front surface and rear surface and including a nanopore having a nano-sized diameter; a reservoir disposed adjacent to a rear surface of the nanopore device; and a power supply unit comprising a first electrode disposed in a front of the nanopore device; a second electrode disposed inside the reservoir; and a third electrode disposed adjacent the nanopore and between the first electrode and the second electrode; as well as a method of using the biomolecule detection apparatus to detect a biomolecule in a sample.

摘要翻译： 一种生物分子检测装置，包括具有前表面和后表面的纳米孔装置，并且包括具有纳米尺寸直径的纳米孔; 设置在所述纳米孔装置的后表面附近的储存器; 以及电源单元，包括设置在所述纳米孔装置的前面的第一电极; 设置在所述储存器内的第二电极; 以及与所述纳米孔相邻并且位于所述第一电极和所述第二电极之间的第三电极; 以及使用生物分子检测装置检测样品中的生物分子的方法。

公开(公告)号：US08288738B2

公开(公告)日：2012-10-16

申请号：US12613118

申请日：2009-11-05

申请人： Seong-ho Cho ,  Dong-ho Lee

发明人： Seong-ho Cho ,  Dong-ho Lee

IPC分类号： G01N21/76 ,  G01T1/10

CPC分类号： G01N21/6452 ,  G01N21/6454 ,  G01N2021/6439 ,  G01N2021/6478 ,  G01N2035/00158

摘要： A substrate for detecting samples includes; a body, and a plurality of micro lenses arranged on the body and configured for attachment to at least one sample, wherein the at least one sample emits fluorescent light, and wherein the plurality of micro lenses condense the fluorescent light emitted from the at least one sample via refraction.

摘要翻译： 用于检测样品的衬底包括： 主体和多个微透镜，其布置在主体上并且被配置为附接到至少一个样品，其中所述至少一个样品发射荧光，并且其中所述多个微透镜将从所述至少一个样品发射的荧光冷凝 样品通过折射。