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    STARCH/RUBBER LATEX COMPOUND AND METHOD FOR MANUFACTURING SAME USING COUPLING REAGENT
    1.
    发明申请
    STARCH/RUBBER LATEX COMPOUND AND METHOD FOR MANUFACTURING SAME USING COUPLING REAGENT 审中-公开
    STARCH / RUBBER LATEX化合物及其使用联合试剂制备相同方法

    公开(公告)号：US20130079441A1

    公开(公告)日：2013-03-28

    申请号：US13297749

    申请日：2011-11-16

    申请人： Hyung Seok Kim ,  Hyun Chul Cho ,  Ur Ryong Cho ,  Seok Min Jang ,  Jong Hyuk Lim

    发明人： Hyung Seok Kim ,  Hyun Chul Cho ,  Ur Ryong Cho ,  Seok Min Jang ,  Jong Hyuk Lim

    IPC分类号： C08L7/00 ,  C08K13/06 ,  C08L7/02

    CPC分类号： C08L21/02 ,  C08L3/02 ,  C08L61/04

    摘要： Disclosed is a rubber composition obtained by chemically blending rubber with a filler, particularly in which Latex rubber is directly blended with a starch solution obtained by gelatinizing starch in water. Herein, as a coupling agent between Latex rubber and starch, resorcinol-formaldehyde is used. By this, a vulcanized rubber compound is prepared. When resorcinol-formaldehyde is used as a coupling agent during the blending of the Latex rubber with the gelatinized starch solution, it is possible to solve the problem of tensile strength lowering caused by low affinity with rubber. Furthermore, it is possible to inhibit starch loss caused by high water-solubility, during the blending of starch in a liquid state. Also, the physical property of the vulcanized rubber compound can be varied according to the amount of the added coupling agent.

    摘要翻译： 公开了通过将橡胶与填料进行化学混合而获得的橡胶组合物，特别是其中乳胶橡胶与淀粉在水中糊化得到的淀粉溶液直接混合。 这里，作为胶乳与淀粉的偶联剂，使用间苯二酚 - 甲醛。 由此制备硫化橡胶化合物。 在胶乳与胶凝淀粉溶液共混过程中使用间苯二酚 - 甲醛作为偶联剂时，可以解决与橡胶的低亲和力引起的拉伸强度降低的问题。 此外，在液态淀粉的共混过程中，可以抑制高水溶性引起的淀粉损失。 而且，硫化橡胶化合物的物理性能可以根据添加的偶联剂的量而变化。

    RESISTOR-BASED SIGMA-DELTA DAC
    2.
    发明申请
    RESISTOR-BASED SIGMA-DELTA DAC 有权
    基于电阻的SIGMA-DELTA DAC

    公开(公告)号：US20130271305A1

    公开(公告)日：2013-10-17

    申请号：US13995156

    申请日：2011-09-30

    申请人： Hyung Seok Kim ,  Yee W. Li ,  Ashoke Ravi ,  Hasnain Lakdawala

    发明人： Hyung Seok Kim ,  Yee W. Li ,  Ashoke Ravi ,  Hasnain Lakdawala

    IPC分类号： H03M3/00 ,  H03M1/78

    CPC分类号： H03M3/50 ,  G09G3/3688 ,  H03M1/00 ,  H03M1/0863 ,  H03M1/12 ,  H03M1/747 ,  H03M1/785 ,  H03M1/808 ,  H03M3/30 ,  H03M3/502

    摘要： An inverter-driven resistor-ladder digital-to-analog (DAC) converter includes a resistor-ladder network that comprises a resistor for each bit signal of a multi-bit input signal. Each resistor of the resistor-ladder network comprises an input end and an output end. The input end of each resistor is coupled to a corresponding bit signal of the multi-bit input signal, and the output end of each resistor is coupled to an output node of the resistor-ladder network. An output voltage is generated at the output node that is based on the multi-bit input signal. In one exemplary embodiment, the multi-bit input signal is a sigma-delta (ΣΔ) modulated multi-bit input signal. In another exemplary embodiment, resistance values of the resistors of the resistor-ladder network are related by a binary weighting. In still another exemplary embodiment, resistance values of the resistors of the resistor-ladder network are substantially equal.

    摘要翻译： 逆变器驱动的电阻梯形数模（DAC）转换器包括一个电阻梯形网络，包括一个多位输入信号的每个位信号的电阻。 电阻梯形网络的每个电阻器包括输入端和输出端。 每个电阻器的输入端耦合到多位输入信号的对应位信号，并且每个电阻器的输出端耦合到电阻梯形网络的输出节点。 在输出节点处产生基于多位输入信号的输出电压。 在一个示例性实施例中，多位输入信号是Σ-Δ（SigmaDelta）调制的多位输入信号。 在另一示例性实施例中，电阻梯形网络的电阻器的电阻值通过二进制加权相关。 在又一示例性实施例中，电阻梯形网络的电阻器的电阻值基本相等。

    Semiconductor memory device and method of operating the same
    3.
    发明授权
    Semiconductor memory device and method of operating the same 有权
    半导体存储器件及其操作方法

    公开(公告)号：US08526239B2

    公开(公告)日：2013-09-03

    申请号：US13096870

    申请日：2011-04-28

    申请人： Hyung Seok Kim

    发明人： Hyung Seok Kim

    IPC分类号： G11C16/06 ,  G11C16/04

    CPC分类号： G11C16/26 ,  G11C16/344

    摘要： A semiconductor memory device includes a memory string coupled to a bit line, a page buffer configured to sense a sensing current of the bit line in an erase verification operation or a program verification operation, and a sensing control circuit configured to differently set a level of the sensing current in the erase verification operation and the program verification operation in order to sense the threshold voltage level of a selected memory cell of the memory string.

    摘要翻译： 半导体存储器件包括耦合到位线的存储器串，配置为在擦除验证操作或程序验证操作中感测位线的感测电流的页缓冲器，以及感测控制电路，其被配置为不同地设置 擦除验证操作中的感测电流和程序验证操作，以便感测存储器串的选定存储单元的阈值电压电平。

    Selective infarcted-tissue-targeting bacteria and use thereof
    8.
    发明授权
    Selective infarcted-tissue-targeting bacteria and use thereof 有权
    选择性梗死组织靶向细菌及其用途

    公开(公告)号：US09339018B2

    公开(公告)日：2016-05-17

    申请号：US13322637

    申请日：2010-05-27

    申请人： Hyon El Choy ,  Jung-Joon Min ,  Hyung Seok Kim ,  Yeongjin Hong

    发明人： Hyon El Choy ,  Jung-Joon Min ,  Hyung Seok Kim ,  Yeongjin Hong

    IPC分类号： A61K48/00 ,  A61K35/74 ,  A61K49/00 ,  A01K67/027 ,  C07K14/255 ,  A61K35/00

    CPC分类号： A01K67/027 ,  A01K2207/12 ,  A01K2227/105 ,  A01K2267/0375 ,  A61K48/0033 ,  A61K2035/11 ,  C07K14/255 ,  C12N2830/001

    摘要： The present invention relates to bacteria which specifically target infarcted tissue and use thereof. The present invention provides a selective infarcted tissue-targeting bacterium for the first time, and can be used in selectively delivering drugs to the infarcted tissue or in selectively imaging the infarcted tissue. The infarcted tissue-targeting bacterium of the present invention can finish treatments by using antibiotics, and therefore, have remarkable advantages as compared to gene therapy using recombinant viruses. The infarcted tissue-targeting bacterium of the present invention have a significantly high affinity and specificity to infarcted myocardium or infarcted brain, thereby significantly reducing undesired transfections in the organs or tissues other than the heart. The gene expression by the infarcted tissue-targeting bacterium of the present invention in infarcted myocardium or infarcted brain is remotely controllable.

    摘要翻译： 本发明涉及特异性靶向梗死组织的细菌及其应用。 本发明首次提供了选择性梗塞的组织靶向细菌，并且可以用于选择性地将药物递送至梗死组织或选择性地成像梗塞组织。 本发明的梗塞组织靶向细菌可以通过使用抗生素来完成治疗，因此与使用重组病毒的基因治疗相比具有显着的优点。 本发明的梗死组织靶向细菌对梗塞的心肌或梗死的脑具有显着高的亲和性和特异性，从而显着减少心脏以外的器官或组织中不期望的转染。 本发明的梗死组织靶向细菌在梗死心肌或梗死的脑中的基因表达是可远程控制的。

    Resistor-based Σ-ΔDAC
    9.
    发明授权
    Resistor-based Σ-ΔDAC 有权
    基于电阻和电阻的DAC

    公开(公告)号：US08941520B2

    公开(公告)日：2015-01-27

    申请号：US13995156

    申请日：2011-09-30

    申请人： Hyung Seok Kim ,  Yee W. Li ,  Ashoke Ravi ,  Hasnain Lakdawala

    发明人： Hyung Seok Kim ,  Yee W. Li ,  Ashoke Ravi ,  Hasnain Lakdawala

    IPC分类号： H03M3/00 ,  H03M1/08 ,  H03M1/80 ,  H03M1/78 ,  H03M1/74 ,  H03M1/00 ,  H03M1/12 ,  G09G3/36

    CPC分类号： H03M3/50 ,  G09G3/3688 ,  H03M1/00 ,  H03M1/0863 ,  H03M1/12 ,  H03M1/747 ,  H03M1/785 ,  H03M1/808 ,  H03M3/30 ,  H03M3/502

    摘要： An inverter-driven resistor-ladder digital-to-analog (DAC) converter includes a resistor-ladder network that comprises a resistor for each bit signal of a multi-bit input signal. Each resistor of the resistor-ladder network comprises an input end and an output end. The input end of each resistor is coupled to a corresponding bit signal of the multi-bit input signal, and the output end of each resistor is coupled to an output node of the resistor-ladder network. An output voltage is generated at the output node that is based on the multi-bit input signal. In one exemplary embodiment, the multi-bit input signal is a sigma-delta (ΣΔ) modulated multi-bit input signal. In another exemplary embodiment, resistance values of the resistors of the resistor-ladder network are related by a binary weighting. In still another exemplary embodiment, resistance values of the resistors of the resistor-ladder network are substantially equal.

    摘要翻译： 逆变器驱动的电阻梯形数模（DAC）转换器包括一个电阻梯形网络，包括一个多位输入信号的每个位信号的电阻。 电阻梯形网络的每个电阻器包括输入端和输出端。 每个电阻器的输入端耦合到多位输入信号的对应位信号，并且每个电阻器的输出端耦合到电阻梯形网络的输出节点。 在输出节点处产生基于多位输入信号的输出电压。 在一个示例性实施例中，多比特输入信号是Σ-Δ（＆Sgr＆amp; Dgr）调制的多位输入信号。 在另一示例性实施例中，电阻梯形网络的电阻器的电阻值通过二进制加权相关。 在又一示例性实施例中，电阻梯形网络的电阻器的电阻值基本相等。

    Semiconductor memory device having improved erase characteristic of memory cells and erase method thereof
    10.
    发明授权
    Semiconductor memory device having improved erase characteristic of memory cells and erase method thereof 有权
    具有改善的存储单元的擦除特性的半导体存储器件及其擦除方法

    公开(公告)号：US08929148B2

    公开(公告)日：2015-01-06

    申请号：US13293391

    申请日：2011-11-10

    申请人： Hyung Seok Kim

    发明人： Hyung Seok Kim

    IPC分类号： G11C11/36

    CPC分类号： G11C16/16 ,  G11C16/0483 ,  G11C16/3409 ,  G11C16/3445

    摘要： A semiconductor memory device includes a plurality of memory blocks configured to include memory cells, a voltage supply circuit configured to supply an erase voltage for an erase operation of a memory block selected from the memory blocks and supply an erase verify voltage and an erase pass voltage for an erase verify operation of the memory block selected from the memory blocks, and a control logic configured to group word lines per specific word lines, when the erase verify operation for the selected memory block is performed, and control the voltage supply circuit so that one or more of the erase verify voltage and the erase pass voltage rise whenever the erase verify operation is performed.

    摘要翻译： 一种半导体存储器件包括：多个存储块，被配置为包括存储单元;电压供给电路，被配置为提供擦除电压，用于从存储块中选择的存储块的擦除操作，并提供擦除验证电压和擦除通过电压 用于从存储块中选择的存储块的擦除验证操作;以及控制逻辑，被配置为当执行所选择的存储块的擦除验证操作时，每个特定字线对字线进行分组，并且控制电压供应电路，使得 只要执行擦除验证操作，擦除验证电压和擦除通过电压中的一个或多个上升。