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    Method of estimating self refresh period of semiconductor memory device
    1.
    发明申请
    Method of estimating self refresh period of semiconductor memory device 有权
    估计半导体存储器件的自刷新周期的方法

    公开(公告)号：US20100302883A1

    公开(公告)日：2010-12-02

    申请号：US12798196

    申请日：2010-03-31

    申请人： Hyung-Dong Kim ,  Byung-Hwan So

    发明人： Hyung-Dong Kim ,  Byung-Hwan So

    IPC分类号： G11C7/00 ,  G11C8/04

    CPC分类号： G11C11/406 ,  G11C8/04 ,  G11C11/40615 ,  G11C2211/4061 ,  G11C2211/4067

    摘要： In a method of estimating a self refresh period of a semiconductor memory device according to an exemplary embodiment, a plurality of internal address signals are reset in response to a refresh reset signal. The plurality of internal address signals are sequentially changed synchronously with an oscillation signal. A refresh completion signal is generated based on the plurality of internal address signals. The self refresh period is detected based on the refresh reset signal and the refresh completion signal.

    摘要翻译： 在根据示例性实施例的估计半导体存储器件的自刷新周期的方法中，响应于刷新复位信号复位多个内部地址信号。 多个内部地址信号与振荡信号同步地顺序地改变。 基于多个内部地址信号产生刷新完成信号。 基于刷新复位信号和刷新完成信号来检测自刷新周期。

    Method of estimating self refresh period of semiconductor memory device
    2.
    发明授权
    Method of estimating self refresh period of semiconductor memory device 有权
    估计半导体存储器件的自刷新周期的方法

    公开(公告)号：US08264904B2

    公开(公告)日：2012-09-11

    申请号：US12798196

    申请日：2010-03-31

    申请人： Hyung-Dong Kim ,  Byung-Hwan So

    发明人： Hyung-Dong Kim ,  Byung-Hwan So

    IPC分类号： G11C7/00

    CPC分类号： G11C11/406 ,  G11C8/04 ,  G11C11/40615 ,  G11C2211/4061 ,  G11C2211/4067

    摘要： In a method of estimating a self refresh period of a semiconductor memory device according to an exemplary embodiment, a plurality of internal address signals are reset in response to a refresh reset signal. The plurality of internal address signals are sequentially changed synchronously with an oscillation signal. A refresh completion signal is generated based on the plurality of internal address signals. The self refresh period is detected based on the refresh reset signal and the refresh completion signal.

    摘要翻译： 在根据示例性实施例的估计半导体存储器件的自刷新周期的方法中，响应于刷新复位信号复位多个内部地址信号。 多个内部地址信号与振荡信号同步地顺序地改变。 基于多个内部地址信号产生刷新完成信号。 基于刷新复位信号和刷新完成信号来检测自刷新周期。

    Pump circuits and methods for integrated circuits including first and second oscillators and first and second pumps
    5.
    发明授权
    Pump circuits and methods for integrated circuits including first and second oscillators and first and second pumps 有权
    包括第一和第二振荡器以及第一和第二泵的集成电路的泵电路和方法

    公开(公告)号：US06724242B2

    公开(公告)日：2004-04-20

    申请号：US10370398

    申请日：2003-02-20

    申请人： Hyung-Dong Kim ,  Chi-Sung Oh

    发明人： Hyung-Dong Kim ,  Chi-Sung Oh

    IPC分类号： G05F302

    CPC分类号： H02M3/073 ,  H02M2001/0032 ,  H02M2003/077 ,  Y02B70/16

    摘要： Boosted voltage generates and methods for an integrated circuit are configured to boost an initial boosted voltage to a first boosted voltage in response to detecting a drop in the initial voltage. The first boosted voltage is then boosted to a second boosted voltage in response to a pulse. The second boosted voltage is then repeatedly boosted to approach the initial boosted voltage in response to an oscillating signal. Accordingly, stable boosted voltages may be generated.

    摘要翻译： 升压电压产生，并且集成电路的方法被配置为响应于检测到初始电压的下降而将初始升压电压升压到第一升压电压。 然后响应于脉冲将第一升压电压升压到第二升压电压。 然后响应于振荡信号，第二升压电压被反复升高以接近初始升压电压。 因此，可能产生稳定的升压电压。

    Boosting voltage level detector for a semiconductor memory device
    6.
    发明授权
    Boosting voltage level detector for a semiconductor memory device 失效
    用于半导体存储器件的升压电压检测器

    公开(公告)号：US5742197A

    公开(公告)日：1998-04-21

    申请号：US341108

    申请日：1994-11-18

    申请人： Hyung-Dong Kim ,  Chan-Jong Park

    发明人： Hyung-Dong Kim ,  Chan-Jong Park

    IPC分类号： H01L27/10 ,  G01R19/165 ,  G11C5/14 ,  G11C8/08 ,  H03K5/08 ,  G05F1/10

    CPC分类号： H03K5/08 ,  G01R19/16519 ,  G11C5/145 ,  G11C8/08

    摘要： A boosting voltage level detector for a semiconductor memory device which utilizes a boosting voltage the level of which is higher than that of a power supply voltage, which includes a pull-up portion and a pull-down portion. In a preferred embodiment, the pull-up portion includes a PMOS transistor and a first NMOS transistor connected in series between the power supply voltage and an output node, and the pull-down portion includes second and third NMOS transistors connected in series between the output node and ground. The PMOS transistor has a gate electrode which is coupled to ground, and thus functions as a current source. The second NMOS transistor has a gate electrode which is coupled to a reference voltage, and thus functions as a resistor. The gate electrodes of the first and third NMOS transistors are commonly coupled to the boosting voltage. The detector further includes an inverter circuit coupled to the output node. The voltage value of the output node rises above the trip point level of the inverter in response to the boosting voltage rising above a predetermined voltage level, and the voltage value of the output node falls below the trip point level in response to the boosting voltage falling below the predetermined voltage level.

    摘要翻译： 一种用于半导体存储器件的升压电压电平检测器，其利用其电平高于包括上拉部分和下拉部分的电源电压的升压电压。 在优选实施例中，上拉部分包括PMOS晶体管和串联连接在电源电压和输出节点之间的第一NMOS晶体管，并且下拉部分包括串联连接在输出端之间的第二和第三NMOS晶体管 节点和地面。 PMOS晶体管具有耦合到地的栅极，因此用作电流源。 第二NMOS晶体管具有耦合到参考电压的栅极，因此用作电阻器。 第一和第三NMOS晶体管的栅电极通常耦合到升压电压。 检测器还包括耦合到输出节点的反相器电路。 响应于升压电压升高到高于预定电压电平，输出节点的电压值高于反相器的跳变点电平，并且输出节点的电压值响应于升压电压下降而下降到跳变点电平以下 低于预定电压电平。

    METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES
    7.
    发明申请
    METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES 有权
    制造半导体器件的方法

    公开(公告)号：US20120052648A1

    公开(公告)日：2012-03-01

    申请号：US13221099

    申请日：2011-08-30

    申请人： Hyung-Shin Kwon ,  Hyung-Dong Kim

    发明人： Hyung-Shin Kwon ,  Hyung-Dong Kim

    IPC分类号： H01L21/02

    CPC分类号： H01L28/60 ,  H01L27/10814 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/90

    摘要： A semiconductor device may include lower electrodes having different heights depending on positions on a substrate. Supporting layer pattern making a contact with the lower electrodes having a relatively large height is provided. The supporting layer pattern is provided between the lower electrodes for supporting the lower electrodes. A dielectric layer is provided on the lower electrodes and the supporting layer pattern. An upper electrode is formed on the dielectric layer and has a planar upper surface. An inter-metal dielectric layer is provided on the upper electrode. A metal contact penetrating through the inter-metal dielectric layer and making a contact with the upper electrode is formed. A bottom portion of the metal contact faces a portion under where the lower electrode having a relatively small height is formed. The device has a higher reliability.

    摘要翻译： 半导体器件可以包括取决于衬底上的位置的具有不同高度的下电极。 提供了与具有相对较大高度的下电极接触的支撑层图案。 支撑层图案设置在用于支撑下电极的下电极之间。 电介质层设置在下电极和支撑层图案上。 在电介质层上形成上电极，具有平坦的上表面。 在上电极上设置金属间介电层。 形成穿过金属间介电层并与上电极接触的金属接触。 金属接触件的底部部分形成在具有较小高度的下部电极下方的部分。 该设备具有较高的可靠性。

    Semiconductor memory device having test address generating circuit and method of testing semiconductor memory device having a test address generating circuit
    8.
    发明授权
    Semiconductor memory device having test address generating circuit and method of testing semiconductor memory device having a test address generating circuit 失效
    具有测试地址产生电路的半导体存储器件和具有测试地址产生电路的半导体存储器件的测试方法

    公开(公告)号：US08051341B2

    公开(公告)日：2011-11-01

    申请号：US12214453

    申请日：2008-06-19

    申请人： Yong-Hwan Cho ,  Hyung-Dong Kim ,  Woo-II Kim

    发明人： Yong-Hwan Cho ,  Hyung-Dong Kim ,  Woo-II Kim

    IPC分类号： G11C29/00

    CPC分类号： G11C29/20 ,  G11C2029/3602

    摘要： A semiconductor memory device includes a test address generating circuit configured on the device. The test address generating circuit generates a plurality of test addresses for a test of the semiconductor memory device in response to at least one externally applied test address generation signal. As a result, the number of DUTs can increase, based on a reduction of required address pins, and manufacturing productivity and test efficiency of semiconductor memory devices can increase.

    摘要翻译： 半导体存储器件包括在该器件上配置的测试地址产生电路。 测试地址产生电路响应于至少一个外部施加的测试地址产生信号，产生用于半导体存储器件测试的多个测试地址。 结果，基于所需地址引脚的减少，DUT的数量可以增加，并且半导体存储器件的制造生产率和测试效率可以增加。

    Semiconductor memory device for enhancing bitline precharge time
    10.
    发明授权
    Semiconductor memory device for enhancing bitline precharge time 失效
    用于增强位线预充电时间的半导体存储器件

    公开(公告)号：US06856563B2

    公开(公告)日：2005-02-15

    申请号：US10659249

    申请日：2003-09-11

    申请人： Hyung-Dong Kim ,  Chi-Sung Oh

    发明人： Hyung-Dong Kim ,  Chi-Sung Oh

    IPC分类号： G11C11/4091 ,  G11C7/12 ,  G11C8/02 ,  G11C11/4094 ,  G11C7/00

    CPC分类号： G11C11/4094 ,  G11C7/12

    摘要： A semiconductor memory device for enhancing bitline precharge time and method for accelerating precharge time in the device is provided which may reduce overall precharging time, in an effort to guarantee proper high speed operations in the semiconductor memory device. In the method, an equalization enable signal may be applied to an equalizer of the device to precharge a bitline pair connected a memory cell, isolation part and sense amplifier of the device. Isolation control signals, to be applied to one or more of the isolation parts, may be delayed by a given time, so that a time of applying the isolation control signals is after a time of applying the equalization enable signal to the equalizer.

    摘要翻译： 提供一种用于增强位线预充电时间的半导体存储器件和用于加速器件中的预充电时间的方法，其可以减少总体预充电时间，以努力保证半导体存储器件中的适当的高速操作。 在该方法中，均衡使能信号可以被施加到器件的均衡器，以对连接存储器单元，器件的隔离部分和读出放大器的位线对进行预充电。 要施加到一个或多个隔离部分的隔离控制信号可以被延迟给定时间，使得施加隔离控制信号的时间是在将均衡使能信号施加到均衡器的时间之后。