Abstract:
A diffused resistor structure and method for fabrication which produces the resistor electrical contacts below the surface of the semiconductor device. The resistor structure includes a resistor region of a first conductivity type surrounded at the surface of the region by a region of a second conductivity. At least two spaced semiconductor electrical contacts of a first conductivity are made to the resistor region. The contacts are below the surface of the resistor structure. Electrical contacts are provided on the surface of the structure spaced from the resistor region and electrically connected to the two spaced semiconductor contacts below the surface of the resistor structure.
Abstract:
THIS INVENTION RELATES GENERALLY TO MONOLITHIC INTEGRATED STRUCTURES INCLUDING THE FABRICATION THEREOF AND, MORE PARTICULARLY, TO A MONOLITHIC INTEGRATED STRUCTURE THAT IS USED TO PROVIDE A MULTIPLICITY OF VARIOUS CIRCUIT INTERCONNECTIONS SO AS TO PERMIT MORE THAN ONE CIRCUIT TO BE MADE FOR EACH STRUCTURE. MANY LOGIC TYPE INTEGRATED STRUCTURES CAN BE FABRICATED FROM A SINGLE MASTER SLICE CONFIGURATION WHICH CONTAINS A NUMBER OF COMPONENTS IN A PATTERN FAVORABLE TO THE FORMATION OF ANY SELECTED LOGIC CIRCUIT FROM A CLASS OF MANY SUCH CIRCUITS. ADDITIONALLY, FABRICATION TECHNIQUES ARE DESCRIBED FOR FACILITATING FORMATION OF THE INTEGRATED CHIP WHICH INCLUDE MASK ALIGNMENT TECHNIQUES, CHIP TESTING TECHNIQUES, CHIP IDENTIFICATION, PROCESS STEP IDENTIFICATION, ENGINEERING CHANGE NUMBER IDENTIFICATION, ETC.
Abstract:
To eliminate parasitic voltage drops to electrodes of semiconductor devices built on a semiconductor chip or wafer, due to the use of an element of a voltage and current supply conductor in common for several such semiconductor devices, a separate path is diffused for each electrode, onto such chip or wafer as a built-up post of the basic semiconductor material of the chip or wafer, and the back surface of the chip or wafer is used as a relatively wide area surface as a voltage supply bus, which may also be connected to a metal base for the double purpose of establishing that surface at some selected known potential and providing a good heat sink for the chip or wafer. Generally, the potential of the metal base may be placed at ground, but need not be.