公开(公告)号：US20200286730A1

公开(公告)日：2020-09-10

申请号：US16811192

申请日：2020-03-06

Applicant: Infineon Technologies AG

Inventor： Iris MODER ,  Bernhard GOLLER ,  Tobias Franz Wolfgang HOECHBAUER ,  Roland RUPP ,  Francisco Javier SANTOS RODRIGUEZ ,  Hans-Joachim SCHULZE

IPC: H01L21/02 ,  H01L21/475 ,  H01L21/4757

Abstract: A semiconductor substrate includes a base portion, an auxiliary layer and a surface layer. The auxiliary layer is formed on the base portion. The surface layer is formed on the auxiliary layer. The surface layer is in contact with a first main surface of the semiconductor substrate. The auxiliary layer has a different electrochemical dissolution efficiency than the base portion and the surface layer. At least a portion of the auxiliary layer and at least a portion of the surface layer are converted into a porous structure. Subsequently, an epitaxial layer is formed on the first main surface.

公开(公告)号：US20240153759A1

公开(公告)日：2024-05-09

申请号：US18407025

申请日：2024-01-08

Applicant: Infineon Technologies AG

Inventor： Iris MODER ,  Bernhard GOLLER ,  Tobias Franz Wolfgang HOECHBAUER ,  Roland RUPP ,  Francisco Javier SANTOS RODRIGUEZ ,  Hans-Joachim SCHULZE

IPC: H01L21/02 ,  H01L21/467 ,  H01L21/475 ,  H01L21/4757 ,  H01L29/739 ,  H01L29/78

CPC classification number: H01L21/02203 ,  H01L21/0203 ,  H01L21/02293 ,  H01L21/02378 ,  H01L21/467 ,  H01L21/475 ,  H01L21/47576 ,  H01L29/7395 ,  H01L29/7802

Abstract: A semiconductor substrate includes a base portion, an auxiliary layer and a surface layer. The auxiliary layer is formed on the base portion. The surface layer is formed on the auxiliary layer. The surface layer is in contact with a first main surface of the semiconductor substrate. The auxiliary layer has a different electrochemical dissolution efficiency than the base portion and the surface layer. At least a portion of the auxiliary layer and at least a portion of the surface layer are converted into a porous structure. Subsequently, an epitaxial layer is formed on the first main surface.

公开(公告)号：US20230154978A1

公开(公告)日：2023-05-18

申请号：US17526490

申请日：2021-11-15

Applicant: Infineon Technologies AG

Inventor： Carsten SCHAEFFER ,  Patrick HANEKAMP ,  Oliver HUMBEL ,  Angelika KOPROWSKI ,  Wolfgang LEHNERT ,  Francisco Javier SANTOS RODRIGUEZ

IPC: H01L29/06 ,  H01L29/40 ,  H01L21/02

CPC classification number: H01L29/0638 ,  H01L29/402 ,  H01L21/0217 ,  H01L21/02118 ,  H01L21/0228

Abstract: A semiconductor device and a method of forming a semiconductor device are provided. In an embodiment, the semiconductor device comprises a device region, an edge termination region surrounding the device region, a first metal feature in the edge termination region, a first conformal ion diffusion barrier layer over the first metal feature, and a first conformal chemical protection layer over the first conformal ion diffusion barrier layer.

公开(公告)号：US20170207124A1

公开(公告)日：2017-07-20

申请号：US15404400

申请日：2017-01-12

Applicant: Infineon Technologies AG

Inventor： Roland RUPP ,  Francisco Javier SANTOS RODRIGUEZ ,  Hans-Joachim SCHULZE

IPC: H01L21/78 ,  H01L29/66 ,  H01L21/322 ,  H01L21/265 ,  H01L21/268

CPC classification number: H01L21/7806 ,  H01L21/02002 ,  H01L21/265 ,  H01L21/268 ,  H01L21/322 ,  H01L29/0834 ,  H01L29/1608 ,  H01L29/32 ,  H01L29/66068 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7397 ,  H01L29/8611

Abstract: Methods of forming a semiconductor device are provided. A method includes introducing impurities into a part of a semiconductor substrate at a first surface of the semiconductor substrate by ion implantation, the impurities being configured to absorb electromagnetic radiation of an energy smaller than a bandgap energy of the semiconductor substrate. The method further includes forming a semiconductor layer on the first surface of the semiconductor substrate. The method further includes irradiating the semiconductor substrate with electromagnetic radiation configured to be absorbed by the impurities and configured to generate local damage of a crystal lattice of the semiconductor substrate. The method further includes separating the semiconductor layer and the semiconductor substrate by thermal processing of the semiconductor substrate and the semiconductor layer, where the thermal processing is configured to cause crack formation along the local damage of the crystal lattice by thermo-mechanical stress.

公开(公告)号：US20200068709A1

公开(公告)日：2020-02-27

申请号：US16550151

申请日：2019-08-23

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim SCHULZE ,  Andre BROCKMEIER ,  Tobias Franz Wolfgang HOECHBAUER ,  Gerhard METZGER-BRUECKL ,  Matteo PICCIN ,  Francisco Javier SANTOS RODRIGUEZ

IPC: H05K1/03 ,  H01L29/16 ,  H01L21/683

Abstract: A carrier configured to be attached to a semiconductor substrate via a first surface comprises a continuous carbon structure defining a first surface of the carrier, and a reinforcing material constituting at least 2 vol-% of the carrier.

公开(公告)号：US20180261487A1

公开(公告)日：2018-09-13

申请号：US15951213

申请日：2018-04-12

Applicant: Infineon Technologies AG

Inventor： Francisco Javier SANTOS RODRIGUEZ ,  Gerald LACKNER ,  Josef UNTERWEGER

IPC: H01L21/683 ,  H01L21/304

Abstract: A wafer arrangement in accordance with various embodiments may include: a wafer; and a wafer support ring, wherein the wafer and the wafer support ring are configured to be releasably coupled to one another so that the wafer support ring can be uncoupled from the wafer without causing damage to the wafer or the wafer support ring.

公开(公告)号：US20220359194A1

公开(公告)日：2022-11-10

申请号：US17869524

申请日：2022-07-20

Applicant: Infineon Technologies AG

Inventor： Iris MODER ,  Bernhard GOLLER ,  Tobias Franz Wolfgang HOECHBAUER ,  Roland RUPP ,  Francisco Javier SANTOS RODRIGUEZ ,  Hans-Joachim SCHULZE

IPC: H01L21/02 ,  H01L21/4757 ,  H01L21/475 ,  H01L21/467

Abstract: A semiconductor substrate includes a base portion, an auxiliary layer and a surface layer. The auxiliary layer is formed on the base portion. The surface layer is formed on the auxiliary layer. The surface layer is in contact with a first main surface of the semiconductor substrate. The auxiliary layer has a different electrochemical dissolution efficiency than the base portion and the surface layer. At least a portion of the auxiliary layer and at least a portion of the surface layer are converted into a porous structure. Subsequently, an epitaxial layer is formed on the first main surface.

公开(公告)号：US20200381256A1

公开(公告)日：2020-12-03

申请号：US16884442

申请日：2020-05-27

Applicant: Infineon Technologies AG

Inventor： Francisco Javier SANTOS RODRIGUEZ ,  Roland RUPP ,  Hans-Joachim SCHULZE

IPC: H01L21/268 ,  H01L21/02 ,  H01L29/165 ,  H01L29/16

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a carbon structure on a handle substrate at a first surface of the handle substrate. The method further includes attaching a first surface of a semiconductor substrate to the first surface of the handle substrate. The method further includes processing the semiconductor substrate and performing a separation process to separate the handle substrate from the semiconductor substrate. The separation process comprises modifying the carbon structure.

公开(公告)号：US20170125407A1

公开(公告)日：2017-05-04

申请号：US15299645

申请日：2016-10-21

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim SCHULZE ,  Franz-Josef NIEDERNOSTHEIDE ,  Frank Dieter PFIRSCH ,  Francisco Javier SANTOS RODRIGUEZ ,  Stephan VOSS ,  Wolfgang WAGNER

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/739 ,  H01L21/8234 ,  H01L27/082 ,  H01L29/49 ,  H01L29/06

CPC classification number: H01L27/088 ,  H01L21/823418 ,  H01L21/82345 ,  H01L21/823475 ,  H01L27/0629 ,  H01L27/082 ,  H01L29/0607 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/4983 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/66363 ,  H01L29/7393 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/749

Abstract: A semiconductor device and a method for producing thereof is provided. The semiconductor device includes a plurality of device cells, each comprising a body region, a source region, and a gate electrode adjacent to the body region and dielectrically insulated from the body region by a gate dielectric; and an electrically conductive gate layer comprising the gate electrodes or electrically connected to the gate electrodes of the plurality of device cells. The gate layer is electrically connected to a gate conductor and includes at least one of an increased resistance region and a decreased resistance region.

公开(公告)号：US20250006814A1

公开(公告)日：2025-01-02

申请号：US18756389

申请日：2024-06-27

Applicant: Infineon Technologies AG

Inventor： Wolfgang LEHNERT ,  Fabian RASINGER ,  Thomas AICHINGER ,  Gerald RESCHER ,  Francisco Javier SANTOS RODRIGUEZ ,  Carsten SCHAEFFER ,  Armin TILKE

IPC: H01L29/51 ,  H01L21/02 ,  H01L21/28 ,  H01L29/16 ,  H01L29/40 ,  H01L29/739 ,  H01L29/78

Abstract: A method for forming an interface layer on a silicon carbide body comprises removing an oxide layer from a surface of a silicon carbide body to obtain a silicon carbide surface. The silicon carbide body comprises a source region of a first conductivity type and a body region of a second conductivity type. The method further comprises after removing the oxide layer, depositing an interface layer directly on the silicon carbide surface. The interface layer has a thickness of less or equal to 15 nm. The method further comprises forming an electrical insulator over the interface layer, and forming a gate electrode over the electrical insulator.