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Patent Agency Ranking
公开(公告)号：US08759207B2
公开(公告)日：2014-06-24
申请号：US13671583
申请日：2012-11-08
Applicant: Infineon Technologies AG
Inventor： Hans-Joachim Barth , Mathias Vaupel , Rainer Steiner , Werner Robl , Jens Pohl , Joem Plagmann , Gottfried Beer
IPC: H01L21/20
CPC classification number: H01L21/76843 , H01L21/76807 , H01L21/76879 , H01L23/49816 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L23/53266 , H01L24/03 , H01L24/10 , H01L24/13 , H01L2224/0401 , H01L2224/13 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01037 , H01L2924/01042 , H01L2924/01044 , H01L2924/01047 , H01L2924/0105 , H01L2924/0106 , H01L2924/01068 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/12042 , H01L2924/14 , H01L2924/15788 , H01L2924/00
Abstract: One or more embodiments relate to a method of forming a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a seed layer over the barrier layer; forming an inhibitor layer over the seed layer; removing a portion of said inhibitor layer to expose a portion of the seed layer; and selectively depositing a fill layer on the exposed seed layer.
Abstract translation: 一个或多个实施例涉及一种形成半导体结构的方法，包括：提供工件; 在工件上形成阻挡层; 在阻挡层上形成种子层; 在种子层上形成抑制层; 去除所述抑制剂层的一部分以暴露所述种子层的一部分; 并且在曝光的种子层上选择性地沉积填充层。
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公开(公告)号：US09658296B2
公开(公告)日：2017-05-23
申请号：US13939113
申请日：2013-07-10
Applicant: Infineon Technologies AG
Inventor： Udo Ausserlechner , Volker Strutz , Jochen Dangelmaier , Rainer Steiner
CPC classification number: G01R33/0047 , B29C70/745 , G01R15/20 , H01L24/48 , H01L2224/4809 , H01L2224/48451 , H01L2224/48465 , H01L2924/00014 , H01L2924/181 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/85399 , H01L2224/05599
Abstract: A current sensor device includes a casing having a cavity and a conductor fixedly mounted to the casing. A semiconductor chip configured to sense a magnetic field is arranged in the cavity. An electrically insulating medium is configured to at least partially fill the cavity of the casing.
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公开(公告)号：US09041226B2
公开(公告)日：2015-05-26
申请号：US13798141
申请日：2013-03-13
Applicant: Infineon Technologies AG
Inventor： Rainer Steiner , Edward Fuergut , Khalil Hosseini , Georg Meyer-Berg , Joachim Mahler
IPC: H01L23/48 , H01L21/00 , H01L23/00 , H01L23/495 , H01L23/31
CPC classification number: H01L23/562 , H01L23/3107 , H01L23/49513 , H01L23/49517 , H01L23/49562 , H01L24/06 , H01L24/24 , H01L24/25 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/82 , H01L24/92 , H01L2224/04105 , H01L2224/06181 , H01L2224/24246 , H01L2224/2518 , H01L2224/2929 , H01L2224/29387 , H01L2224/32245 , H01L2224/73267 , H01L2224/92144 , H01L2224/92244 , H01L2924/07802 , H01L2924/10252 , H01L2924/10253 , H01L2924/10271 , H01L2924/10329 , H01L2924/12042 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/00
Abstract: In various embodiments, a chip arrangement is provided. The chip arrangement may include a chip carrier and a chip mounted on the chip carrier. The chip may include at least two chip contacts and an insulating adhesive between the chip and the chip carrier to adhere the chip to the chip carrier. The at least two chip contacts may be electrically coupled to the chip carrier.
Abstract translation: 在各种实施例中，提供了芯片布置。 芯片布置可以包括芯片载体和安装在芯片载体上的芯片。 芯片可以包括至少两个芯片触点和芯片与芯片载体之间的绝缘粘合剂，以将芯片粘附到芯片载体上。 所述至少两个芯片触点可以电耦合到芯片载体。
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公开(公告)号：US08786085B2
公开(公告)日：2014-07-22
申请号：US13671573
申请日：2012-11-08
Applicant: Infineon Technologies AG
Inventor： Hans-Joachim Barth , Mathias Vaupel , Rainer Steiner , Werner Robl , Jens Pohl , Joern Plagmann , Gottfried Beer
IPC: H01L23/48
CPC classification number: H01L21/76843 , H01L21/76807 , H01L21/76879 , H01L23/49816 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L23/53266 , H01L24/03 , H01L24/10 , H01L24/13 , H01L2224/0401 , H01L2224/13 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01037 , H01L2924/01042 , H01L2924/01044 , H01L2924/01047 , H01L2924/0105 , H01L2924/0106 , H01L2924/01068 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/12042 , H01L2924/14 , H01L2924/15788 , H01L2924/00
Abstract: One or more embodiments relate to a semiconductor structure, comprising: a barrier layer overlying a workpiece surface; a seed layer overlying the barrier layer; an inhibitor layer overlying said seed layer, the inhibitor layer having a opening exposing a portion of the seed layer, and a fill layer overlying the exposed portion of the seed layer.
Abstract translation: 一个或多个实施例涉及半导体结构，包括：覆盖工件表面的阻挡层; 覆盖阻挡层的种子层; 覆盖所述种子层的抑制剂层，所述抑制剂层具有暴露所述种子层的一部分的开口以及覆盖所述种子层的暴露部分的填充层。
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公开(公告)号：US20140264950A1
公开(公告)日：2014-09-18
申请号：US13798141
申请日：2013-03-13
Applicant: INFINEON TECHNOLOGIES AG
Inventor： Rainer Steiner , Edward Fuergut , Khalil Hosseini , Georg Meyer-Berg , Joachim Mahler
IPC: H01L23/00
CPC classification number: H01L23/562 , H01L23/3107 , H01L23/49513 , H01L23/49517 , H01L23/49562 , H01L24/06 , H01L24/24 , H01L24/25 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/82 , H01L24/92 , H01L2224/04105 , H01L2224/06181 , H01L2224/24246 , H01L2224/2518 , H01L2224/2929 , H01L2224/29387 , H01L2224/32245 , H01L2224/73267 , H01L2224/92144 , H01L2224/92244 , H01L2924/07802 , H01L2924/10252 , H01L2924/10253 , H01L2924/10271 , H01L2924/10329 , H01L2924/12042 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/00
Abstract: In various embodiments, a chip arrangement is provided. The chip arrangement may include a chip carrier and a chip mounted on the chip carrier. The chip may include at least two chip contacts and an insulating adhesive between the chip and the chip carrier to adhere the chip to the chip carrier. The at least two chip contacts may be electrically coupled to the chip carrier.
Abstract translation: 在各种实施例中，提供了芯片布置。 芯片布置可以包括芯片载体和安装在芯片载体上的芯片。 芯片可以包括至少两个芯片触点和芯片与芯片载体之间的绝缘粘合剂，以将芯片粘附到芯片载体上。 所述至少两个芯片触点可以电耦合到芯片载体。
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