公开(公告)号：US10741402B2

公开(公告)日：2020-08-11

申请号：US15692495

申请日：2017-08-31

Applicant: Infineon Technologies AG

Inventor： Paul Frank ,  Gretchen Adema ,  Thomas Bertaud ,  Michael Ehmann ,  Eric Graetz ,  Kamil Karlovsky ,  Evelyn Napetschnig ,  Werner Robl ,  Tobias Schmidt ,  Joachim Seifert ,  Frank Wagner ,  Stefan Woehlert

IPC: H01L23/00 ,  H01L21/285 ,  H01L29/861

Abstract: An electronic device, an electronic module comprising the electronic device and methods for fabricating the same are disclosed. In one example, the electronic device includes a semiconductor substrate and a metal stack disposed on the semiconductor substrate, wherein the metal stack comprises a first layer, wherein the first layer comprises NiSi.

公开(公告)号：US20140242374A1

公开(公告)日：2014-08-28

申请号：US13774624

申请日：2013-02-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Johann Strasser ,  Thomas Kunstmann ,  Manfred Frank ,  Werner Robl ,  Maximilian Krug ,  Simon Faiss ,  Matthias Mueller

IPC: H01L23/14 ,  B05D7/00 ,  C25D7/12 ,  B32B3/26

CPC classification number: H01L23/14 ,  B05D7/52 ,  B32B3/26 ,  C23C18/1644 ,  C23C18/1651 ,  C23C18/32 ,  C23C18/50 ,  C25D7/12 ,  C25D7/123 ,  H01L23/3733 ,  H01L23/49866 ,  H01L23/53238 ,  H01L2924/0002 ,  Y10T428/249956 ,  Y10T428/249957 ,  Y10T428/24997 ,  H01L2924/00

Abstract: Various methods, apparatuses and devices relate to porous metal layers on a substrate which are three-dimensionally coated. In one embodiment, a porous metal layer is deposited over a substrate. The porous metal layer can be three-dimensionally coated with a coating material.

Abstract translation: 各种方法，装置和装置涉及三维涂覆在基底上的多孔金属层。 在一个实施例中，多孔金属层沉积在衬底上。 多孔金属层可以用涂料三维涂覆。

公开(公告)号：US10446469B2

公开(公告)日：2019-10-15

申请号：US15217383

申请日：2016-07-22

Applicant: Infineon Technologies AG

Inventor： Thomas Detzel ,  Johann Gross ,  Robert Illing ,  Maximilian Krug ,  Sven Gustav Lanzerstorfer ,  Michael Nelhiebel ,  Werner Robl ,  Michael Rogalli ,  Stefan Woehlert

IPC: H01L23/00 ,  H01L23/373 ,  H01L23/532 ,  H01L21/288 ,  H01L21/48

Abstract: A semiconductor device includes a base element and a copper element over the base element. The copper element includes a layer stack having at least two copper layers and at least one intermediate conductive layer of a material different from copper. The at least two copper layers and the at least one intermediate conductive layer are alternately stacked over each other.

公开(公告)号：US08786085B2

公开(公告)日：2014-07-22

申请号：US13671573

申请日：2012-11-08

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Barth ,  Mathias Vaupel ,  Rainer Steiner ,  Werner Robl ,  Jens Pohl ,  Joern Plagmann ,  Gottfried Beer

IPC: H01L23/48

CPC classification number: H01L21/76843 ,  H01L21/76807 ,  H01L21/76879 ,  H01L23/49816 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L24/03 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/0106 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/00

Abstract: One or more embodiments relate to a semiconductor structure, comprising: a barrier layer overlying a workpiece surface; a seed layer overlying the barrier layer; an inhibitor layer overlying said seed layer, the inhibitor layer having a opening exposing a portion of the seed layer, and a fill layer overlying the exposed portion of the seed layer.

Abstract translation: 一个或多个实施例涉及半导体结构，包括：覆盖工件表面的阻挡层; 覆盖阻挡层的种子层; 覆盖所述种子层的抑制剂层，所述抑制剂层具有暴露所述种子层的一部分的开口以及覆盖所述种子层的暴露部分的填充层。

公开(公告)号：US11615963B2

公开(公告)日：2023-03-28

申请号：US16926162

申请日：2020-07-10

Applicant: Infineon Technologies AG

Inventor： Paul Frank ,  Gretchen Adema ,  Thomas Bertaud ,  Michael Ehmann ,  Eric Graetz ,  Kamil Karlovsky ,  Evelyn Napetschnig ,  Werner Robl ,  Tobias Schmidt ,  Joachim Seifert ,  Frank Wagner ,  Stefan Woehlert

IPC: H01L23/00 ,  H01L21/285 ,  H01L29/861

Abstract: An electronic device, an electronic module comprising the electronic device and methods for fabricating the same are disclosed. In one example, the electronic device includes a semiconductor substrate and a metal stack disposed on the semiconductor substrate, wherein the metal stack comprises a first layer, wherein the first layer comprises NiSi.

公开(公告)号：US20180082848A1

公开(公告)日：2018-03-22

申请号：US15692495

申请日：2017-08-31

Applicant: Infineon Technologies AG

Inventor： Paul Frank ,  Gretchen Adema ,  Thomas Bertaud ,  Michael Ehmann ,  Eric Graetz ,  Kamil Karlovsky ,  Evelyn Napetschnig ,  Werner Robl ,  Tobias Schmidt ,  Joachim Seifert ,  Frank Wagner ,  Stefan Woehlert

IPC: H01L21/285 ,  H01L23/00 ,  H01L29/861

Abstract: An electronic device, an electronic module comprising the electronic device and methods for fabricating the same are disclosed. In one example, the electronic device includes a semiconductor substrate and a metal stack disposed on the semiconductor substrate, wherein the metal stack comprises a first layer, wherein the first layer comprises NiSi.

公开(公告)号：US20160329263A1

公开(公告)日：2016-11-10

申请号：US15217383

申请日：2016-07-22

Applicant: Infineon Technologies AG

Inventor： Thomas Detzel ,  Johann Gross ,  Robert Illing ,  Maximilian Krug ,  Sven Gustav Lanzerstorfer ,  Michael Nelhiebel ,  Werner Robl ,  Michael Rogalli ,  Stefan Woehlert

IPC: H01L23/373 ,  H01L21/48

CPC classification number: H01L23/3735 ,  H01L21/2885 ,  H01L21/4882 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a base element and a copper element over the base element. The copper element includes a layer stack having at least two copper layers and at least one intermediate conductive layer of a material different from copper. The at least two copper layers and the at least one intermediate conductive layer are alternately stacked over each other.

Abstract translation: 半导体器件包括在基底元件上的基底元件和铜元件。 铜元件包括具有至少两个铜层的层堆叠和至少一个不同于铜的材料的中间导电层。 所述至少两个铜层和所述至少一个中间导电层彼此交替堆叠。

公开(公告)号：US08759207B2

公开(公告)日：2014-06-24

申请号：US13671583

申请日：2012-11-08

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Barth ,  Mathias Vaupel ,  Rainer Steiner ,  Werner Robl ,  Jens Pohl ,  Joem Plagmann ,  Gottfried Beer

IPC: H01L21/20

CPC classification number: H01L21/76843 ,  H01L21/76807 ,  H01L21/76879 ,  H01L23/49816 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L24/03 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/0106 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/00

Abstract: One or more embodiments relate to a method of forming a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a seed layer over the barrier layer; forming an inhibitor layer over the seed layer; removing a portion of said inhibitor layer to expose a portion of the seed layer; and selectively depositing a fill layer on the exposed seed layer.

Abstract translation: 一个或多个实施例涉及一种形成半导体结构的方法，包括：提供工件; 在工件上形成阻挡层; 在阻挡层上形成种子层; 在种子层上形成抑制层; 去除所述抑制剂层的一部分以暴露所述种子层的一部分; 并且在曝光的种子层上选择性地沉积填充层。

公开(公告)号：US20200343094A1

公开(公告)日：2020-10-29

申请号：US16926162

申请日：2020-07-10

Applicant: Infineon Technologies AG

Inventor： Paul Frank ,  Gretchen Adema ,  Thomas Bertaud ,  Michael Ehmann ,  Eric Graetz ,  Kamil Karlovsky ,  Evelyn Napetschnig ,  Werner Robl ,  Tobias Schmidt ,  Joachim Seifert ,  Frank Wagner ,  Stefan Woehlert

IPC: H01L21/285 ,  H01L23/00 ,  H01L29/861

Abstract: An electronic device, an electronic module comprising the electronic device and methods for fabricating the same are disclosed. In one example, the electronic device includes a semiconductor substrate and a metal stack disposed on the semiconductor substrate, wherein the metal stack comprises a first layer, wherein the first layer comprises NiSi.

公开(公告)号：US10648096B2

公开(公告)日：2020-05-12

申请号：US14948463

申请日：2015-11-23

Applicant: Infineon Technologies AG

Inventor： Werner Robl ,  Michael Melzl ,  Manfred Schneegans ,  Bernhard Weidgans ,  Franziska Haering

IPC: C25D5/50 ,  C25D17/12 ,  C25D3/38 ,  C25D3/48 ,  C25D3/46 ,  C25D3/12 ,  C25D3/52 ,  C25D3/32 ,  C25D15/00 ,  C25D7/12 ,  H01L21/288 ,  H01L23/532

Abstract: An electrolyte may be provided. The electrolyte may include at least one additive configured to decompose or evaporate at a temperature above approximately 100° C., and a water soluble metal salt, and the electrolyte may be free from carbon nanotubes. In various embodiments, a method of forming a metal layer may be provided: The method may include depositing a metal layer on a carrier using an electrolyte, wherein the electrolyte may include at least one additive configured to decompose or evaporate at a temperature above approximately 100° C. and a water soluble metal salt, wherein the electrolyte is free from carbon nanotubes; and annealing the metal layer to form a metal layer comprising a plurality of pores. In various embodiments, a semiconductor device may be provided. The semiconductor device may include a metal layer including a plurality of pores, wherein the plurality of pores may be formed in the metal layer as remnants of an additive having resided in the plurality of pores and having at least partially decomposed or evaporated. To keep a high elasticity over a wide temperature range (up to 450° C.), an adhesion layer may stabilize the metal grain boundaries and may fix dislocation gliding inside metal grains. In various embodiments, a metal layer is provided. The metal layer may include a plurality of pores having ellipsoidal or spheroidal shape.