公开(公告)号：US10275853B2

公开(公告)日：2019-04-30

申请号：US14687001

申请日：2015-04-15

Applicant: Intel Corporation

Inventor： Ramanathan Sethuraman ,  Arojit Roychowdhury ,  Ajaya V. Durg ,  Rajeev D. Muralidhar

IPC: G06T1/20 ,  G06T1/60

Abstract: The present disclosure describes techniques related to media caching. A media hub device may include a media hub device configured to execute an operation on a current frame of media having a frame period. The media hub device may include a cache configured to provide, to a media accelerator of the media hub device, data associated with the frame period of the current frame.

公开(公告)号：US20160267883A1

公开(公告)日：2016-09-15

申请号：US14644767

申请日：2015-03-11

Applicant: Intel Corporation

Inventor： Vasudev Bibikar ,  Rajesh Poornachandran ,  Ajaya V. Durg ,  Arpit Shah ,  Anil K. Sabbavarapu ,  Nabil F. Kerkiz ,  Quang T. Le ,  Ryan R. Pinto ,  Moorthy Rajesh ,  James A. Bish ,  Ranjani Sridharan

IPC: G09G5/36 ,  G09G5/395 ,  G09G5/00 ,  G09G5/393

CPC classification number: G09G5/36 ,  G09G5/39 ,  G09G5/395 ,  G09G2320/103 ,  G09G2330/021 ,  G09G2360/121 ,  G09G2360/125

Abstract: Technologies for low-power display refresh standby include a computing device with a display such as an LCD panel. The computing device may include a system-on-a-chip (SoC) with a processor, I/O subsystem, display controller, and memory. When the computing device determines that a display image is static, the computing device enters a low-power display refresh standby mode, powering down unneeded components of the SoC such as processor cores, peripheral devices, and memory other than a dedicated display buffer. The display controller may access the dedicated display buffer via the I/O subsystem and output the image to the display. The computing device may power down the I/O subsystem and the dedicated display buffer when a display controller FIFO is full of image data, and periodically power on the I/O subsystem and display buffer to fill the display controller FIFO. Other embodiments are described and claimed.

Abstract translation: 用于低功率显示刷新待机的技术包括具有诸如LCD面板的显示器的计算设备。 计算设备可以包括具有处理器，I / O子系统，显示控制器和存储器的片上系统（SoC）。 当计算设备确定显示图像是静态时，计算设备进入低功率显示刷新待机模式，为诸如处理器核心，外围设备和专用显示缓冲器之外的存储器的SoC的不需要的组件供电。 显示控制器可以通过I / O子系统访问专用显示缓冲区，并将图像输出到显示器。 当显示控制器FIFO充满图像数据时，计算设备可能会关闭I / O子系统和专用显示缓冲区，并周期性地打开I / O子系统和显示缓冲区以填充显示控制器FIFO。 描述和要求保护其他实施例。

公开(公告)号：US20190155370A1

公开(公告)日：2019-05-23

申请号：US16252816

申请日：2019-01-21

Applicant: Intel Corporation

Inventor： Sundar Ramani ,  Arvind Raman ,  Arvind Mandhani ,  Ashish V. Choubal ,  Kalyan Muthukumar ,  Ajaya V. Durg ,  Samudyatha Chakki

IPC: G06F1/3287 ,  G06F1/3296 ,  G06F1/3203 ,  G06F12/0804 ,  G06F12/084 ,  G06F12/128 ,  G06F12/0831 ,  G06F12/0808 ,  G06F1/324 ,  G06F1/3234 ,  G06F12/0815

Abstract: In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.

公开(公告)号：US09665153B2

公开(公告)日：2017-05-30

申请号：US14221696

申请日：2014-03-21

Applicant: Intel Corporation

Inventor： Sundar Ramani ,  Arvind Raman ,  Arvind Mandhani ,  Ashish V. Choubal ,  Kalyan Muthukumar ,  Ajaya V. Durg ,  Samudyatha Chakki

IPC: G06F1/32 ,  G06F12/0815 ,  G06F12/0804 ,  G06F12/084 ,  G06F12/0811

CPC classification number: G06F1/3287 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3275 ,  G06F1/3296 ,  G06F12/0804 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/128 ,  G06F2212/1028 ,  G06F2212/314 ,  G06F2212/621 ,  G06F2212/69 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/152 ,  Y02D10/172 ,  Y02D50/20

Abstract: In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.

公开(公告)号：US10963038B2

公开(公告)日：2021-03-30

申请号：US16252816

申请日：2019-01-21

Applicant: Intel Corporation

Inventor： Sundar Ramani ,  Arvind Raman ,  Arvind Mandhani ,  Ashish V. Choubal ,  Kalyan Muthukumar ,  Ajaya V. Durg ,  Samudyatha Chakki

IPC: G06F1/32 ,  G06F1/3287 ,  G06F1/3203 ,  G06F1/3296 ,  G06F12/0815 ,  G06F12/0804 ,  G06F12/084 ,  G06F1/324 ,  G06F1/3234 ,  G06F12/0808 ,  G06F12/0831 ,  G06F12/128 ,  G06F12/0811 ,  G06F12/12

Abstract: In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.

公开(公告)号：US10474219B2

公开(公告)日：2019-11-12

申请号：US15529792

申请日：2015-11-30

Applicant: Intel Corporation

Inventor： Arojit Roychowdhury ,  Ramanathan Sethuraman ,  Ajaya V. Durg ,  Rakesh A. Ughreja

IPC: G06F1/3287 ,  G06F1/3225 ,  G06F1/324 ,  G06F1/3234 ,  G06F1/3296 ,  G11C5/14 ,  G06F15/78 ,  G06F1/3237

Abstract: Methods and apparatus to permit a system low power consumption state when CPU (Central Processing Unit) or generically any compute element is active are described. In an embodiment, a fabric and a memory controller are caused to enter a low power consumption state at least partially in response to a determination that the fabric and the memory controller are idle. The entry into the low power consumption state occurs while a compute element, coupled to the fabric and the memory controller, is in an active state. Other embodiments are also disclosed and claimed.

公开(公告)号：US09620088B2

公开(公告)日：2017-04-11

申请号：US14644767

申请日：2015-03-11

Applicant: Intel Corporation

Inventor： Vasudev Bibikar ,  Rajesh Poornachandran ,  Ajaya V. Durg ,  Arpit Shah ,  Anil K. Sabbavarapu ,  Nabil F. Kerkiz ,  Quang T. Le ,  Ryan R. Pinto ,  Moorthy Rajesh ,  James A. Bish ,  Ranjani Sridharan

IPC: G09G5/36 ,  G09G5/395 ,  G09G5/39

CPC classification number: G09G5/36 ,  G09G5/39 ,  G09G5/395 ,  G09G2320/103 ,  G09G2330/021 ,  G09G2360/121 ,  G09G2360/125

Abstract: Technologies for low-power display refresh standby include a computing device with a display such as an LCD panel. The computing device may include a system-on-a-chip (SoC) with a processor, I/O subsystem, display controller, and memory. When the computing device determines that a display image is static, the computing device enters a low-power display refresh standby mode, powering down unneeded components of the SoC such as processor cores, peripheral devices, and memory other than a dedicated display buffer. The display controller may access the dedicated display buffer via the I/O subsystem and output the image to the display. The computing device may power down the I/O subsystem and the dedicated display buffer when a display controller FIFO is full of image data, and periodically power on the I/O subsystem and display buffer to fill the display controller FIFO. Other embodiments are described and claimed.

公开(公告)号：US20160307291A1

公开(公告)日：2016-10-20

申请号：US14687001

申请日：2015-04-15

Applicant: INTEL CORPORATION

Inventor： Ramanathan Sethuraman ,  Arojit Roychowdhury ,  Ajaya V. Durg ,  Rajeev D. Muralidhar

IPC: G06T1/60 ,  G06T1/20

CPC classification number: G06T1/60 ,  G06T1/20

Abstract: The present disclosure describes techniques related to media caching. A media hub device may include a media hub device configured to execute an operation on a current frame of media having a frame period. The media hub device may include a cache configured to provide, to a media accelerator of the media hub device, data associated with the frame period of the current frame.

Abstract translation: 本公开描述了与媒体缓存相关的技术。 媒体集线器设备可以包括被配置为对具有帧周期的媒体的当前帧执行操作的媒体集线器设备。 媒体集线器设备可以包括被配置为向媒体集线器设备的媒体加速器提供与当前帧的帧周期相关联的数据的高速缓存。

公开(公告)号：US10282344B2

公开(公告)日：2019-05-07

申请号：US15122575

申请日：2015-06-04

Applicant: Intel Corporation

Inventor： Sundar Iyer ,  Rajasekaran Andiappan ,  Ajaya V. Durg ,  Kenneth P. Foust ,  Bruce L. Fleming

IPC: G06F13/40 ,  G06F13/42 ,  G06F1/3287 ,  G06F13/26 ,  G06F13/364

Abstract: In one example a sensor module comprises at least one sensor and a controller communicatively coupled to the at least one sensor by a communication bus, the controller comprising logic, at least partially including hardware logic, configured to generate a signal to configure the at least one sensor in a notify power state mode and place the signal on a communication bus coupled to the at least one sensor. Other examples may be described.

公开(公告)号：US10198065B2

公开(公告)日：2019-02-05

申请号：US15494625

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Sundar Ramani ,  Arvind Raman ,  Arvind Mandhani ,  Ashish V. Choubal ,  Kalyan Muthukumar ,  Ajaya V. Durg ,  Samudyatha Chakki

IPC: G06F1/32 ,  G06F12/0815 ,  G06F12/0804 ,  G06F12/084 ,  G06F12/0808 ,  G06F12/0831 ,  G06F12/128 ,  G06F12/0811

Abstract: In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.