公开(公告)号：US20230238368A1

公开(公告)日：2023-07-27

申请号：US18128952

申请日：2023-03-30

Applicant: Intel Corporation

Inventor： Chong ZHANG ,  Cheng XU ,  Junnan ZHAO ,  Ying WANG ,  Meizi JIAO

IPC: H01L25/16 ,  H01L23/538 ,  H01L23/498 ,  H01L21/56 ,  H01L23/528

CPC classification number: H01L25/16 ,  H01L23/5386 ,  H01L28/40 ,  H01L23/49811 ,  H01L21/568 ,  H01L23/528 ,  H01L2224/16265 ,  H01L2224/1623

Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a die having a first surface and an opposing second surface; a capacitor having a surface, wherein the surface of the capacitor is coupled to the first surface of the die; and a conductive pillar coupled to the first surface of the die. In some embodiments, a microelectronic assembly may include a capacitor in a first dielectric layer; a conductive pillar in the first dielectric layer; a first die having a surface in the first dielectric layer; and a second die having a surface in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the surface of the second die is coupled to the capacitor, to the surface of the first die, and to the conductive pillar.

公开(公告)号：US20200006239A1

公开(公告)日：2020-01-02

申请号：US16024717

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Chong ZHANG ,  Krishna BHARATH

IPC: H01L23/538 ,  H01L25/16 ,  H01L23/13 ,  H01L51/10 ,  H01L23/367 ,  H01L23/373 ,  H01F27/28 ,  H01L21/48 ,  H01L51/00 ,  H01L23/00

Abstract: Embodiments herein relate to integrating FIVR switching circuitry into a substrate that has a first side and a second side opposite the first side, where the first side of the substrate to electrically couple with a die and to provide voltage to the die and the second side of the substrate is to couple with an input voltage source. In embodiments, the FIVR switching circuitry may be printed onto the substrate using OFET, CNT, or other transistor technology, or may be included in a separate die that is incorporated within the substrate.

公开(公告)号：US20190295937A1

公开(公告)日：2019-09-26

申请号：US15927047

申请日：2018-03-20

Applicant: Intel Corporation

Inventor： Chong ZHANG ,  Ying WANG ,  Cheng XU ,  Hongxia FENG ,  Meizi JIAO ,  Junnan ZHAO ,  Yikang DENG

IPC: H01L23/498 ,  C23C18/26 ,  H05K1/11 ,  H01L23/00 ,  H01L21/48

Abstract: Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a trace disposed on a conductive layer. The semiconductor package has one or more adhesion anchoring points and a plurality of portions on the trace. An adhesion anchoring point is between two portions on the trace. A surface roughness of an adhesion anchoring point is greater than a surface roughness of a portion on the trace. The trace may be a high-speed input/output (HSIO) trace. The semiconductor package may include via pads disposed on each end of the trace, and a dielectric disposed on the trace. The dielectric is patterned to form openings on the dielectric that expose second portions on the trace. The dielectric remains over the portions. The semiconductor package may have a chemical treatment disposed on the exposed openings on the trace to form the adhesion anchoring points.

公开(公告)号：US20200312771A1

公开(公告)日：2020-10-01

申请号：US16366661

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Bai NIE ,  Gang DUAN ,  Srinivas PIETAMBARAM ,  Jesse JONES ,  Yosuke KANAOKA ,  Hongxia FENG ,  Dingying XU ,  Rahul MANEPALLI ,  Sameer PAITAL ,  Kristof DARMAWIKARTA ,  Yonggang LI ,  Meizi JIAO ,  Chong ZHANG ,  Matthew TINGEY ,  Jung Kyu HAN ,  Haobo CHEN

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

Abstract: A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.

公开(公告)号：US20240088052A1

公开(公告)日：2024-03-14

申请号：US18513015

申请日：2023-11-17

Applicant: Intel Corporation

Inventor： Bai NIE ,  Gang DUAN ,  Srinivas PIETAMBARAM ,  Jesse JONES ,  Yosuke KANAOKA ,  Hongxia FENG ,  Dingying XU ,  Rahul MANEPALLI ,  Sameer PAITAL ,  Kristof DARMAWIKARTA ,  Yonggang LI ,  Meizi JIAO ,  Chong ZHANG ,  Matthew TINGEY ,  Jung Kyu HAN ,  Haobo CHEN

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/214 ,  H01L2924/3511 ,  H01L2924/381

Abstract: A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.

公开(公告)号：US20190274217A1

公开(公告)日：2019-09-05

申请号：US15910288

申请日：2018-03-02

Applicant: Intel Corporation

Inventor： Chong ZHANG ,  Ying WANG ,  Junnan ZHAO ,  Cheng XU ,  Yikang DENG

IPC: H05K1/16 ,  H01F27/28 ,  H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H05K3/00 ,  H05K3/42 ,  H01F41/04

Abstract: Embodiments may include inductors with embedded magnetic cores and methods of making such inductors. In an embodiment, an integrated circuit package may include an integrated circuit die with a multi-phase voltage regulator electrically coupled to the integrated circuit die. In such embodiments, the multi-phase voltage regulator may include a substrate core and a plurality of inductors. The inductors may include a conductive through-hole disposed through the substrate core and a plugging layer comprising a dielectric material surrounding the conductive through-hole. In an embodiment, a magnetic sheath is formed around the plugging layer. In an embodiment, the magnetic sheath is separated from the plated through hole by the plugging layer. Additionally, a first layer comprising a dielectric material may be disposed over a first surface of the magnetic sheath, and a second layer comprising a dielectric material may be disposed over a second surface of the magnetic sheath.

公开(公告)号：US20190272936A1

公开(公告)日：2019-09-05

申请号：US15911549

申请日：2018-03-05

Applicant: Intel Corporation

Inventor： Chong ZHANG ,  Cheng XU ,  Ying WANG ,  Junnan ZHAO ,  Meizi JIAO ,  Yikang DENG

IPC: H01F27/24 ,  G05F1/10 ,  H01L49/02 ,  H01F41/02

Abstract: Embodiments include inductors with embedded magnetic cores and methods of forming such inductors. Some embodiments may include an integrated circuit package that utilizes such inductors. For example, the integrated circuit package may include an integrated circuit die and a multi-phase voltage regulator electrically coupled to the integrated circuit die. In an embodiment, the multi-phase voltage regulator includes a substrate core and a plurality of inductors in the substrate core. In an embodiment, the inductors may include a conductive loop in and around the substrate core. In an embodiment, the conductive loops are electrically coupled to a voltage out line. Embodiments may also include a magnetic core surrounded by the conductive loops. The magnetic core is separated from surfaces of the conductive loops by the substrate core

公开(公告)号：US20240405006A1

公开(公告)日：2024-12-05

申请号：US18805232

申请日：2024-08-14

Applicant: Intel Corporation

Inventor： Chong ZHANG ,  Cheng XU ,  Junnan ZHAO ,  Ying WANG ,  Meizi JIAO

IPC: H01L25/16 ,  H01L21/56 ,  H01L23/498 ,  H01L23/528 ,  H01L23/538

Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a die having a first surface and an opposing second surface; a capacitor having a surface, wherein the surface of the capacitor is coupled to the first surface of the die; and a conductive pillar coupled to the first surface of the die. In some embodiments, a microelectronic assembly may include a capacitor in a first dielectric layer; a conductive pillar in the first dielectric layer; a first die having a surface in the first dielectric layer; and a second die having a surface in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the surface of the second die is coupled to the capacitor, to the surface of the first die, and to the conductive pillar.

公开(公告)号：US20220117089A1

公开(公告)日：2022-04-14

申请号：US17560004

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Chong ZHANG ,  Ying WANG ,  Junnan ZHAO ,  Cheng XU ,  Yikang DENG

IPC: H05K1/16 ,  H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H05K3/00 ,  H05K3/42 ,  H01F41/04 ,  H01F27/28 ,  H01F17/00

Abstract: Embodiments may include inductors with embedded magnetic cores and methods of making such inductors. In an embodiment, an integrated circuit package may include an integrated circuit die with a multi-phase voltage regulator electrically coupled to the integrated circuit die. In such embodiments, the multi-phase voltage regulator may include a substrate core and a plurality of inductors. The inductors may include a conductive through-hole disposed through the substrate core and a plugging layer comprising a dielectric material surrounding the conductive through-hole. In an embodiment, a magnetic sheath is formed around the plugging layer. In an embodiment, the magnetic sheath is separated from the plated through hole by the plugging layer. Additionally, a first layer comprising a dielectric material may be disposed over a first surface of the magnetic sheath, and a second layer comprising a dielectric material may be disposed over a second surface of the magnetic sheath.

公开(公告)号：US20190304889A1

公开(公告)日：2019-10-03

申请号：US15941903

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Meizi JIAO ,  Chong ZHANG ,  Hongxia FENG ,  Kevin MCCARTHY

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H05K1/11 ,  H05K3/40 ,  H05K3/06

Abstract: Techniques for fabricating a package substrate comprising a via, a conductive line, and a pad are described. The package substrate can be included in a semiconductor package. For one technique, a package substrate includes: a pad in a dielectric layer; a via; and a conductive line. The via and the conductive line can be part of a structure. Alternatively, the conductive line can be adjacent to the via. The dielectric layer can include a pocket above the pad. One or more portions of the via may be formed in the pocket above the pad. Zero or more portions of the via can be formed on the dielectric layer outside the pocket. In some scenarios, no pad is above the via. The package substrate provides several advantages. One exemplary advantage is that the package substrate can assist with increasing an input/output density per millimeter per layer (IO/mm/layer) of the package substrate.