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公开(公告)号:US12133322B2
公开(公告)日:2024-10-29
申请号:US17133113
申请日:2020-12-23
Applicant: Intel Corporation
Inventor: Jaejin Lee , Isaac Simpson , Dong-Ho Han , Jose Salazar Delgado , Arturo Navarro Alvarez
IPC: H05K1/02
CPC classification number: H05K1/0225 , H05K1/0298 , H05K2201/093
Abstract: Electromagnetic interference (EMI) shields having attenuation interfaces are disclosed. A disclosed example EMI shield includes side walls defining sides of the EMI shield, and an attenuation interface to be placed into contact with a circuit board. The attenuation interface includes an inner perimeter having an EMI absorber and an outer perimeter having a metal backing to at least partially surround the EMI absorber.
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公开(公告)号:US12074368B2
公开(公告)日:2024-08-27
申请号:US17754149
申请日:2019-12-27
Applicant: INTEL CORPORATION
Inventor: Denica Larsen , Dong-Ho Han , Kwan Ho Lee , Shantanu Kulkarni , Jaejin Lee
Abstract: An electronic computing device with a self-shielding antenna. An electronic computing device may include a frame, an antenna, and an antenna shielding. The frame includes a top cover and a bottom cover. Electronic components are included in a space formed between the top cover and the bottom cover. The antenna is for wireless transmission and reception and included in the frame near an edge of the frame. The antenna shielding is disposed around the antenna for providing electro-magnetic shielding from radio frequency (RE) noises generated from the electronic components included in the frame. The antenna shielding may be a metal wall disposed between the top cover and the bottom cover around the antenna. The frame may be a metallic frame and may include a cut-out in the top cover and the bottom cover above and below the antenna, and a non-metallic cover may be provided in the cut-out.
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公开(公告)号:US20230187839A1
公开(公告)日:2023-06-15
申请号:US17547858
申请日:2021-12-10
Applicant: Intel Corporation
Inventor: Seong-Youp John Suh , Tae Young Yang , Kwan Ho Lee , Dong-Ho Han
CPC classification number: H01Q13/18 , H01Q9/0407 , H01P3/121
Abstract: A substrate integrated waveguide (SIW) cavity antenna is described that enables dual frequency and broadband operation, as well as enhanced protection from radio frequency interference (RFI) that may be present within an electronic device environment. The SIW cavity antenna includes a capacitively-coupled feed that is disposed within the volume of the SIW cavity antenna, which is enclosed on four sides via a set of electrically-conductive plates. The SIW cavity antenna radiates using the remaining two open sides as apertures. The SIW cavity antenna may include a meander line radiator to facilitate the operation of a second frequency band, as well as the use of a tuning stub to further enhance the impedance bandwidth.
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公开(公告)号:US20220394884A1
公开(公告)日:2022-12-08
申请号:US17890310
申请日:2022-08-18
Applicant: Intel Corporation
Inventor: Kwan Ho Lee , Dong-Ho Han , Jose Luis Trigueros Soto , Sean Lawrence Molloy , Tae Young Yang , Seong-Youp Suh , Vinay Ramachandra Gowda
Abstract: In some embodiments, a computer system chassis comprises a chassis side having an antenna portion and a fan portion. The antenna portion is located closer to an antenna located on an external surface of the chassis side than the fan portion. The antenna and fan portions comprise ventilation holes that provide for the venting of heated air from the chassis interior to the surrounding environment. In some embodiments, the ventilation holes in the antenna portion are thicker than the ventilation holes in the fan portion. The thicker ventilation holes provide an adequate level of EMI shielding for the antenna from platform noise generated by components (CPUs, GPUs, memories, etc.) located in the chassis interior. In other embodiments, the antenna portion comprises alternating positive and negative cross pattern ventilation holes and provides an adequate level of EMI shielding with the antenna portion ventilation holes having the same thickness as the fan portion ventilation holes.
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公开(公告)号:US10454163B2
公开(公告)日:2019-10-22
申请号:US15713286
申请日:2017-09-22
Applicant: Intel Corporation
Inventor: JaeJin Lee , Dong-Ho Han , Hao-Han Hsu
Abstract: Embodiments include apparatuses, methods, and systems including an electronic apparatus including an inductor within a circuit package affixed to a printed circuit board (PCB) having a ground layer, where the ground layer includes a mesh area that is substantially void along a contour of the inductor. An electronic apparatus may include a circuit package with an inductor, and a PCB, where the circuit package may be affixed to the PCB. The PCB may have a plurality of layers including a ground layer and a power layer, where the ground layer may be between the power layer and the inductor. The ground layer may include a mesh area that may be substantially void along a contour of the inductor within the circuit package. Other embodiments may also be described and claimed.
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公开(公告)号:US11749606B2
公开(公告)日:2023-09-05
申请号:US17371293
申请日:2021-07-09
Applicant: Intel Corporation
Inventor: Amit Kumar Jain , Sameer Shekhar , Chin Lee Kuan , Kevin Joseph Doran , Dong-Ho Han
IPC: H01L23/538 , H01L49/02 , H01L23/00
CPC classification number: H01L23/5381 , H01L23/5383 , H01L28/20 , H01L28/40 , H01L23/5384 , H01L24/16 , H01L2224/16225
Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate; a bridge, embedded in the package substrate, wherein the bridge includes an integral passive component, and wherein a surface of the bridge include first contacts in a first interconnect area and second contacts in a second interconnect area; a first die coupled to the passive component via the first contacts in the first interconnect area; and a second die coupled to the second contacts in the second interconnect area.
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公开(公告)号:US20190304915A1
公开(公告)日:2019-10-03
申请号:US16446920
申请日:2019-06-20
Applicant: Intel Corporation
Inventor: Amit Kumar Jain , Sameer Shekhar , Chin Lee Kuan , Kevin Joseph Doran , Dong-Ho Han
IPC: H01L23/538 , H01L49/02
Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate; a bridge, embedded in the package substrate, wherein the bridge includes an integral passive component, and wherein a surface of the bridge include first contacts in a first interconnect area and second contacts in a second interconnect area; a first die coupled to the passive component via the first contacts in the first interconnect area; and a second die coupled to the second contacts in the second interconnect area.
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公开(公告)号:US10403581B2
公开(公告)日:2019-09-03
申请号:US15721729
申请日:2017-09-29
Applicant: Intel Corporation
Inventor: Jaejin Lee , Hao-Han Hsu , Chung-Hao J. Chen , Dong-Ho Han
IPC: H01L23/552 , H01L21/48 , H01L23/498 , H01L21/56 , H01L23/14 , H01L23/31 , H01L21/02 , H05K1/02 , H01L23/66 , H01L23/00 , H01L23/16
Abstract: Electronic device packages utilizing a stiffener coupled to a substrate with a magnetic lossy bonding layer to attenuate or absorb electromagnetic signals such as radio frequency interference (RFI) along with related systems and method are disclosed.
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公开(公告)号:US20190103366A1
公开(公告)日:2019-04-04
申请号:US15721729
申请日:2017-09-29
Applicant: Intel Corporation
Inventor: Jaejin Lee , Hao-Han Hsu , Chung-Hao J. Chen , Dong-Ho Han
IPC: H01L23/552 , H01L21/56 , H01L23/14 , H01L23/31 , H01L21/48 , H01L21/02 , H05K1/02 , H01L23/498
CPC classification number: H01L23/552 , H01L21/02227 , H01L21/4857 , H01L21/563 , H01L23/142 , H01L23/16 , H01L23/3114 , H01L23/49838 , H01L23/562 , H01L23/66 , H01L2223/6677 , H01L2924/10253 , H01L2924/14 , H01L2924/153 , H01L2924/15311 , H01L2924/3025 , H01L2924/3511 , H05K1/0271
Abstract: Electronic device packages utilizing a stiffener coupled to a substrate with a magnetic lossy bonding layer to attenuate or absorb electromagnetic signals such as radio frequency interference (RFI) along with related systems and method are disclosed.
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公开(公告)号:US20190097313A1
公开(公告)日:2019-03-28
申请号:US15713286
申请日:2017-09-22
Applicant: Intel Corporation
Inventor: JaeJin Lee , Dong-Ho Han , Hao-Han Hsu
CPC classification number: H01Q1/52 , H01Q1/242 , H01Q1/273 , H01Q1/38 , H01Q1/48 , H05K1/0225 , H05K3/3436 , H05K2201/09681 , H05K2201/10098
Abstract: Embodiments include apparatuses, methods, and systems including an electronic apparatus including an inductor within a circuit package affixed to a printed circuit board (PCB) having a ground layer, where the ground layer includes a mesh area that is substantially void along a contour of the inductor. An electronic apparatus may include a circuit package with an inductor, and a PCB, where the circuit package may be affixed to the PCB. The PCB may have a plurality of layers including a ground layer and a power layer, where the ground layer may be between the power layer and the inductor. The ground layer may include a mesh area that may be substantially void along a contour of the inductor within the circuit package. Other embodiments may also be described and claimed.
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