公开(公告)号：US20200004154A1

公开(公告)日：2020-01-02

申请号：US16569903

申请日：2019-09-13

Applicant: International Business Machines Corporation

Inventor： Gerald Bartley ,  Matthew Doyle ,  Darryl Becker ,  Mark Jeanson

IPC: G03F7/20 ,  G03F1/38 ,  G03F7/038 ,  G03F7/039 ,  G03F7/16 ,  G03F7/26 ,  G03F7/40 ,  H05K3/40

Abstract: The present invention provides a process and a structure of forming conductive vias using a light guide. In an exemplary embodiment, the process includes providing a via in a base material in a direction perpendicular to a plane of the base material, applying a photoresist layer to an interior surface of the via, inserting a light guide into the via, exposing, by the light guide, a portion of the photoresist layer to light, thereby resulting in an exposed portion of the photoresist layer and an unexposed portion of the photoresist layer, removing a portion of the photoresist layer, and plating an area of the via, where the photoresist has been removed, with a metal, thereby resulting in a portion of the via plated with metal and a portion of the via not plated with metal.

公开(公告)号：US20190155154A1

公开(公告)日：2019-05-23

申请号：US15819349

申请日：2017-11-21

Applicant: International Business Machines Corporation

Inventor： Matthew Kelly ,  Mark Jeanson ,  Joseph Kuczynski

IPC: G03F7/032 ,  G03F7/028 ,  G03F7/038 ,  G03F7/039 ,  H01L21/48 ,  B23K35/22

Abstract: Disclosed herein are solder mask formulations that include a liquid photo imageable solution and a solution of functionalized diamondoids. Also disclosed are semiconductor fabrication methods that include applying a described solder mask formulation to a semiconductor device.

公开(公告)号：US10157527B1

公开(公告)日：2018-12-18

申请号：US15824592

申请日：2017-11-28

Applicant: International Business Machines Corporation

Inventor： Gerald Bartley ,  Darryl Becker ,  Matthew S. Doyle ,  Mark Jeanson

IPC: G08B13/24 ,  G06F11/30 ,  G06F21/82 ,  H05K7/02 ,  G08B29/04 ,  G06F11/34

Abstract: An embossed printed circuit board (PCB) for intrusion detection including a first security trace layer comprising a first serpentine trace monitored by a security sense circuit; a second security trace layer comprising a second serpentine trace monitored by the security sense circuit; a protected circuitry layer comprising circuitry protected from intrusion by the first security trace layer and the second security trace layer; and at least one embossed edge, wherein the at least one embossed edge comprises a fixed bend in at least one PCB layer, and wherein the fixed bend displaces at least one point of the at least one PCB layer a distance at least equivalent to a thickness of the at least one PCB layer.

公开(公告)号：US10481496B2

公开(公告)日：2019-11-19

申请号：US15635374

申请日：2017-06-28

Applicant: International Business Machines Corporation

Inventor： Gerald Bartley ,  Matthew Doyle ,  Darryl Becker ,  Mark Jeanson

IPC: G03F7/20 ,  G03F1/38 ,  G03F7/038 ,  G03F7/039 ,  G03F7/16 ,  G03F7/26 ,  G03F7/40 ,  H05K3/40

Abstract: The present invention provides a process and a structure of forming conductive vias using a light guide. In an exemplary embodiment, the process includes providing a via in a base material in a direction perpendicular to a plane of the base material, applying a photoresist layer to an interior surface of the via, inserting a light guide into the via, exposing, by the light guide, a portion of the photoresist layer to light, thereby resulting in an exposed portion of the photoresist layer and an unexposed portion of the photoresist layer, removing a portion of the photoresist layer, and plating an area of the via, where the photoresist has been removed, with a metal, thereby resulting in a portion of the via plated with metal and a portion of the via not plated with metal.

公开(公告)号：US20190004428A1

公开(公告)日：2019-01-03

申请号：US15635374

申请日：2017-06-28

Applicant: International Business Machines Corporation

Inventor： Gerald Bartley ,  Matthew Doyle ,  Darryl Becker ,  Mark Jeanson

IPC: G03F7/20 ,  G03F7/038 ,  G03F7/039 ,  G03F7/16 ,  G03F7/26 ,  G03F7/40 ,  G03F1/38 ,  H05K3/40

Abstract: The present invention provides a process and a structure of forming conductive vias using a light guide. In an exemplary embodiment, the process includes providing a via in a base material in a direction perpendicular to a plane of the base material, applying a photoresist layer to an interior surface of the via, inserting a light guide into the via, exposing, by the light guide, a portion of the photoresist layer to light, thereby resulting in an exposed portion of the photoresist layer and an unexposed portion of the photoresist layer, removing a portion of the photoresist layer, and plating an area of the via, where the photoresist has been removed, with a metal, thereby resulting in a portion of the via plated with metal and a portion of the via not plated with metal.

公开(公告)号：US10834828B2

公开(公告)日：2020-11-10

申请号：US15881205

申请日：2018-01-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Gerald Bartley ,  Darryl Becker ,  Matthew Doyle ,  Mark Jeanson

IPC: G03F1/20 ,  G03F7/20 ,  H05K3/30 ,  H01F41/04 ,  H01F17/00 ,  H01F27/28 ,  G02B6/46 ,  H01B1/02 ,  H01F27/06 ,  H01G2/06 ,  H05K1/11 ,  H05K1/18 ,  H05K3/40 ,  G03F1/00

Abstract: A method for forming passive electrical devices that includes depositing a photo reactive layer over a sidewall of a via that extends through a printed circuit board; inserting a light pipe having a mask configured to provide a passive electronic device geometry within the via to an entire depth of the via; and exposing the photo reactive layer to radiation provided by the light pipe to provide a pattern having the passive electronic device geometry on the sidewall of the via.

公开(公告)号：US10712664B2

公开(公告)日：2020-07-14

申请号：US16569903

申请日：2019-09-13

Applicant: International Business Machines Corporation

Inventor： Gerald Bartley ,  Matthew Doyle ,  Darryl Becker ,  Mark Jeanson

IPC: G03F7/20 ,  H05K3/42 ,  G03F1/38 ,  G03F7/038 ,  G03F7/039 ,  G03F7/16 ,  G03F7/26 ,  G03F7/40 ,  H05K3/40

Abstract: The present invention provides a process and a structure of forming conductive vias using a light guide. In an exemplary embodiment, the process includes providing a via in a base material in a direction perpendicular to a plane of the base material, applying a photoresist layer to an interior surface of the via, inserting a light guide into the via, exposing, by the light guide, a portion of the photoresist layer to light, thereby resulting in an exposed portion of the photoresist layer and an unexposed portion of the photoresist layer, removing a portion of the photoresist layer, and plating an area of the via, where the photoresist has been removed, with a metal, thereby resulting in a portion of the via plated with metal and a portion of the via not plated with metal.

公开(公告)号：US20190239358A1

公开(公告)日：2019-08-01

申请号：US15881205

申请日：2018-01-26

Applicant: International Business Machines Corporation

Inventor： Gerald Bartley ,  Darryl Becker ,  Matthew Doyle ,  Mark Jeanson

IPC: H05K3/30 ,  H05K3/40 ,  H05K1/18 ,  H05K1/11 ,  H01B1/02 ,  G02B6/46 ,  H01F27/06 ,  H01G2/06

Abstract: A method for forming passive electrical devices that includes depositing a photo reactive layer over a sidewall of a via that extends through a printed circuit board; inserting a light pipe having a mask configured to provide a passive electronic device geometry within the via to an entire depth of the via; and exposing the photo reactive layer to radiation provided by the light pipe to provide a pattern having the passive electronic device geometry on the sidewall of the via.

公开(公告)号：US11864327B2

公开(公告)日：2024-01-02

申请号：US17006305

申请日：2020-08-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Gerald Bartley ,  Darryl Becker ,  Matthew Doyle ,  Mark Jeanson

IPC: H01F27/28 ,  H05K3/30 ,  H01F41/04 ,  H01F17/00 ,  G03F7/00 ,  G02B6/46 ,  H01B1/02 ,  H01F27/06 ,  H01G2/06 ,  H05K1/11 ,  H05K1/18 ,  H05K3/40 ,  G03F1/62

CPC classification number: H05K3/301 ,  G02B6/46 ,  G03F7/70733 ,  H01B1/02 ,  H01F17/0013 ,  H01F17/0033 ,  H01F27/06 ,  H01F27/2804 ,  H01F41/042 ,  H01F41/046 ,  H01G2/06 ,  H05K1/115 ,  H05K1/184 ,  H05K3/4038 ,  G03F1/62 ,  H01F2017/002 ,  H01F2017/004 ,  H01F2027/065

Abstract: An inductor structure is provided that is positioned within a via of a printed circuit board. The inductor structure includes a via extending through a printed circuit board. The inductor structure includes at least one coil of an electrically conductive material beginning at a first opening to the via continuously present on a sidewall of the via encircling a center of the via extending to a second opening of the via opposite the first opening of the via. It further includes at least electrode present in contact with an end of the coil at said first or second opening.

公开(公告)号：US10739679B2

公开(公告)日：2020-08-11

申请号：US16458930

申请日：2019-07-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Matthew Kelly ,  Mark Jeanson ,  Joseph Kuczynski

IPC: G03F7/032 ,  G03F7/028 ,  G03F7/038 ,  G03F7/027 ,  B23K35/22 ,  G03F7/039 ,  H01L21/48 ,  G03F7/004 ,  B23K35/02 ,  B23K35/36 ,  G03F7/26

Abstract: Disclosed herein are solder mask formulations that include a liquid photo imagable solution and a solution of functionalized diamondoids. Also disclosed are semiconductor fabrication methods that include applying a described solder mask formulation to a semiconductor device.