Forming conductive vias using a light guide

    公开(公告)号:US10712664B2

    公开(公告)日:2020-07-14

    申请号:US16569903

    申请日:2019-09-13

    Abstract: The present invention provides a process and a structure of forming conductive vias using a light guide. In an exemplary embodiment, the process includes providing a via in a base material in a direction perpendicular to a plane of the base material, applying a photoresist layer to an interior surface of the via, inserting a light guide into the via, exposing, by the light guide, a portion of the photoresist layer to light, thereby resulting in an exposed portion of the photoresist layer and an unexposed portion of the photoresist layer, removing a portion of the photoresist layer, and plating an area of the via, where the photoresist has been removed, with a metal, thereby resulting in a portion of the via plated with metal and a portion of the via not plated with metal.

    CHIP INTERCONNECT DEVICES
    7.
    发明申请

    公开(公告)号:US20200314997A1

    公开(公告)日:2020-10-01

    申请号:US16368926

    申请日:2019-03-29

    Abstract: An interconnect device may include a first center conductor of a first material that has a first durometer. The first center conductor may be surrounded by a first inner dielectric ring, which may be surrounded by a conductive region of a second material having a second durometer. The second durometer may be different from the first durometer. The conductive region may have a first end that defines a first plane and a second end that defines a second plane. An outer dielectric ring may surround the conductive region. The first center conductor may have a first bulb and a second bulb, the first bulb may extend in a direction away from the second plane and beyond the first plane, and the second bulb may extend in a direction away from the first plane and beyond the second plane.

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