公开(公告)号：US11245020B2

公开(公告)日：2022-02-08

申请号：US16745100

申请日：2020-01-16

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Michael A. Guillorn ,  Terence Hook ,  Robert R. Robison ,  Reinaldo Vega ,  Tenko Yamashita

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L29/06 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/786

Abstract: One example of an apparatus includes a conducting channel region. The conducting channel region includes a plurality of epitaxially grown, in situ doped conducting channels arranged in a spaced apart relation relative to each other. A source positioned at a first end of the conducting channel region, and a drain positioned at a second end of the conducting channel region. A gate surrounds all sides of the conducting channel region and fills in spaces between the plurality of epitaxially grown, in situ doped conducting channels.

公开(公告)号：US10283374B2

公开(公告)日：2019-05-07

申请号：US14882549

申请日：2015-10-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam ,  Robert R. Robison

IPC: H01L23/62 ,  H01L21/324 ,  H01L27/02 ,  H01L29/866 ,  H01L29/861

Abstract: Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an N+ diffusion on a substrate and a P+ diffusion on the substrate. The P+ diffusion is in electrical contact with the N+ diffusion. The method further includes forming a device between the N+ diffusion and the P+ diffusion. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.

公开(公告)号：US10243041B2

公开(公告)日：2019-03-26

申请号：US15626433

申请日：2017-06-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hari V. Mallela ,  Robert R. Robison ,  Reinaldo A. Vega ,  Rajasekhar Venigalla

IPC: H01L21/8234 ,  H01L29/06 ,  H01L21/764 ,  H01L27/12 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78 ,  H01L21/311 ,  H01L29/10 ,  H01L21/28

Abstract: A fin field effect transistor device with air gaps, including a source/drain layer on a substrate, one or more vertical fin(s) in contact with source/drain layer, a gate metal fill that forms a portion of a gate structure on each of the one or more vertical fin(s), and a bottom void space between the source/drain layer and the gate metal fill.

公开(公告)号：US10147725B2

公开(公告)日：2018-12-04

申请号：US14968134

申请日：2015-12-14

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Gauri Karve ,  Derrick Liu ,  Robert R. Robison ,  Gen Tsutsui ,  Reinaldo A. Vega ,  Koji Watanabe

IPC: H01L21/8234 ,  H01L27/092 ,  H01L29/49 ,  H01L29/161 ,  H01L29/16 ,  H01L21/02 ,  H01L29/40

Abstract: A method of making a semiconductor device comprises forming a first channel region comprising a first channel region material and a second channel region comprising a second channel region material; disposing a gate dielectric on the first channel region and second channel region; depositing a work function modifying material on the gate dielectric; disposing a mask over the work function modifying material deposited on the gate dielectric disposed on the first channel region; removing the work function modifying material from the unmasked gate dielectric disposed on the second channel region; removing the mask from the work function modifying material deposited on the gate dielectric disposed on the first channel region; forming a first gate electrode on the work function modifying material deposited on the first channel region and forming a second gate electrode on the gate dielectric disposed on the second channel region.

公开(公告)号：US20180254329A1

公开(公告)日：2018-09-06

申请号：US15446636

申请日：2017-03-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael A. Guillorn ,  Terence B. Hook ,  Nicolas J. Loubet ,  Robert R. Robison ,  Reinaldo A. Vega

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L29/165

CPC classification number: H01L29/6681 ,  H01L29/0665 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/7849 ,  H01L29/785

Abstract: A method is presented for forming a nanosheet metal oxide semiconductor field effect transistor (MOSFET) structure. The method includes forming a heteroepitaxial film stack including at least one sacrificial layer and at least one channel layer, patterning the heteroepitaxial film stack, forming a dummy gate stack with sidewall spacers, and forming a cladded or embedded epitaxial source/drain material along the patterned heteroepitaxial film stack sidewalls. The method further includes removing the dummy gate stack, partially removing the at least one sacrificial layer, and forming a replacement gate stack.

公开(公告)号：US20180219082A1

公开(公告)日：2018-08-02

申请号：US15417312

申请日：2017-01-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael A. Guillorn ,  Terence B. Hook ,  Robert R. Robison ,  Reinaldo A. Vega ,  Rajasekhar Venigalla

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/66553 ,  B82Y10/00 ,  H01L21/28088 ,  H01L21/28194 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/78651 ,  H01L29/78696

Abstract: A method of forming a nanosheet device, including forming a channel stack on a substrate, where the channel stack includes at least one nanosheet channel layer and at least one sacrificial release layer, forming a stack cover layer on at least a portion of the channel stack, forming a dummy gate on at least a portion of the stack cover layer, wherein at least a portion of the at least one nanosheet channel layer and at least one sacrificial release layer is exposed on opposite sides of the dummy gate, removing at least a portion of the at least one sacrificial release layer on each side of the dummy gate to form a sacrificial supporting rib, and forming an inner spacer layer on exposed portions of the at least one nanosheet channel layer and at least one sacrificial supporting rib.

公开(公告)号：US09859421B1

公开(公告)日：2018-01-02

申请号：US15271842

申请日：2016-09-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Robert R. Robison ,  Reinaldo A. Vega ,  Rajasekhar Venigalla

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/49

CPC classification number: H01L29/7827 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66666

Abstract: A method is presented for forming a vertical field effect transistor (VFET) structure. The method includes forming a plurality of vertical fins over a substrate, forming a dummy gate between the plurality of vertical fins, removing the dummy gate with a subway etch to define a gate cavity, and forming a high-k metal gate (HKMG) stack within the gate cavity. The method further includes forming the first and second source/drain regions before the HKMG stack. The method further includes defining the HKMG stack by a replacement metal gate (RMG) process, the RMG process defined in part by the subway etch. The subway etch enables removal of the dummy gate from a side portion of the VFET structure.

公开(公告)号：US20170179254A1

公开(公告)日：2017-06-22

申请号：US15180499

申请日：2016-06-13

Applicant: International Business Machines Corporation

Inventor： Gauri Karve ,  Robert R. Robison ,  Reinaldo A. Vega

IPC: H01L29/66 ,  H01L29/16 ,  H01L29/161 ,  H01L27/092 ,  H01L29/20 ,  H01L29/205 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/165

CPC classification number: H01L29/66537 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0638 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/20 ,  H01L29/205 ,  H01L29/36 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method includes removing a top portion of a substrate after implantation of a punch through stopper into the substrate; epitaxially growing undoped material on the substrate, thereby forming a channel; filling a top portion of the channel with an intermediate implant forming a vertically bi-modal dopant distribution, with one doping concentration peak in the top portion of the channel and another doping concentration peak in the punch through stopper; and patterning fins into the channel and the punch though stopper to form a finFET structure.

公开(公告)号：US09337088B2

公开(公告)日：2016-05-10

申请号：US14302757

申请日：2014-06-12

Applicant: International Business Machines Corporation

Inventor： William F. Clark, Jr. ,  Robert R. Robison ,  Hung H. Tran

IPC: H01L21/768 ,  H01L49/02 ,  H01L23/367 ,  H01L23/522

CPC classification number: H01L21/76877 ,  H01L23/3677 ,  H01L23/5225 ,  H01L23/5228 ,  H01L27/0802 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An semiconductor structure, method of fabrication therefor, and design structure therefor is provided. A thermal grid is formed over at least a portion of a substrate. An insulating layer is formed over at least a portion of the thermal grid. A resistor is formed over at least a portion of the insulating layer. A buried interconnect is connected to the thermal grid via at least one contact. The buried interconnect is adapted to receive thermal energy from the thermal grid via the at least one contact.

Abstract translation: 提供了一种半导体结构，其制造方法及其设计结构。 在基板的至少一部分上形成热格栅。 在热网格的至少一部分上形成绝缘层。 在绝缘层的至少一部分上形成电阻器。 埋地互连通过至少一个触点连接到热电网。 埋入的互连件适于经由至少一个触点从热电网接收热能。

公开(公告)号：US09190418B2

公开(公告)日：2015-11-17

申请号：US14217572

申请日：2014-03-18

Applicant: International Business Machines Corporation

Inventor： Anthony I. Chou ,  Murshed M. Chowdhury ,  Arvind Kumar ,  Robert R. Robison

IPC: H01L21/76 ,  H01L27/12 ,  H01L29/66 ,  H01L21/84 ,  H01L21/324 ,  H01L21/225 ,  H01L21/265 ,  H01L29/167

CPC classification number: H01L27/1203 ,  H01L21/225 ,  H01L21/265 ,  H01L21/324 ,  H01L21/84 ,  H01L29/165 ,  H01L29/167 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636

Abstract: After forming source/drain trenches within a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate, portions of the trenches adjacent channel regions of a semiconductor structure are covered either by sacrificial spacers formed on sidewalls of the trenches or by photoresist layer portions. The sacrificial spacers or photoresist layer portions shield portions of the top semiconductor layer underneath the trenches from subsequent ion implantation for forming junction butting. The ion implantation regions thus are confined only in un-shielded, sublayered portions of the top semiconductor layer that are away from the channel regions of the semiconductor structure. The width of the ion implantation regions are controlled such that the implanted dopants do not diffuse into the channel regions during subsequent thermal cycles so as to suppress the short channel effects.

Abstract translation: 在绝缘体上半导体（SOI）衬底的顶部半导体层中形成源极/漏极沟槽之后，半导体结构的相邻沟道区的沟槽的部分被形成在沟槽的侧壁上的牺牲隔离物或由光刻胶层 部分。 牺牲间隔物或光致抗蚀剂层部分屏蔽沟槽下方的顶部半导体层的部分以及后续的离子注入以形成结对接。 因此，离子注入区仅限于远离半导体结构的沟道区的顶部半导体层的未屏蔽的亚层部分。 控制离子注入区域的宽度，使得注入的掺杂剂在随后的热循环期间不扩散到沟道区域中，以便抑制短沟道效应。