公开(公告)号：US20190385854A1

公开(公告)日：2019-12-19

申请号：US16547948

申请日：2019-08-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： QING CAO ,  SHU-JEN HAN ,  NING LI ,  JIANSHI TANG

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/40 ,  B82Y10/00 ,  H01L21/3205 ,  H01L29/78 ,  H01L29/08 ,  H01L21/265 ,  H01L29/51 ,  H01L29/49

Abstract: A method of forming a semiconductor device includes forming a channel layer on a substrate. A gate dielectric is deposited on the channel layer, and a mask is patterned on the gate dielectric. An exposed portion of the gate dielectric is removed to expose a first source/drain region and a second source/drain region of the channel layer. A first source/drain contact is formed on the first source/drain region and a second source/drain contact is formed on the second source/drain region. A cap layer is formed over the first source/drain contact and the second source/drain contact, and the mask is removed. Spacers are formed adjacent to sidewalls of the first source/drain contact and the second source/drain contact. An oxide region is formed in the cap layer and a carbon material is deposited on an exposed portion of the gate dielectric.

公开(公告)号：US20170084837A1

公开(公告)日：2017-03-23

申请号：US15196197

申请日：2016-06-29

Applicant: International Business Machines Corporation

Inventor： QING CAO ,  Kangguo Cheng ,  Zhengwen Li ,  Fei Liu

IPC: H01L49/00 ,  H01L27/092 ,  H01L21/465 ,  H01L21/02 ,  H01L29/423 ,  H01L21/306

CPC classification number: B81B3/0086 ,  B81B7/0058 ,  B81B2203/0307 ,  B81B2203/033 ,  B81C1/00039 ,  B81C1/00698 ,  B81C2201/017 ,  B81C2203/0764 ,  B82Y10/00 ,  C08K5/34 ,  G06N3/0635 ,  H01L21/00 ,  H01L21/02263 ,  H01L21/30625 ,  H01L21/465 ,  H01L27/092 ,  H01L29/42316 ,  H01L49/00

Abstract: An electromechanical device comprises a substrate structure, a set of electrodes, one or more anchor trenches, and one or more multi-faced components. For example, each of the one or more multi-faced components comprises an isolation region formed on a first portion of the surface of the component, a high resistance region formed on a second portion of the surface of the component, and a low resistance region formed on a third portion of the surface of the component. For example, the synapse device is configured to provide an analog resistive output, ranging between the high resistance region and the low resistance region, from at least one of the set of electrodes in response to a pulsed voltage input to at least another one of the set of electrodes.

公开(公告)号：US20180364192A1

公开(公告)日：2018-12-20

申请号：US15626363

申请日：2017-06-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： QING CAO ,  HARIKLIA DELIGIANNI ,  FEI LIU

IPC: G01N27/327 ,  G01N27/30 ,  G01N27/36 ,  C23C16/40 ,  C23C16/56 ,  C23C16/02 ,  A61B5/145 ,  A61B5/1468 ,  A61B5/00

Abstract: Embodiments of the invention are directed to a system for detecting neurotransmitters. A non-limiting example of the system includes a porous electrode. A system can also include a pH sensor attached to the porous electrode, wherein the pH sensor includes a sensing electrode and a reference electrode. The system can also include electronic circuitry in communication with the pH sensor.

公开(公告)号：US20180090324A1

公开(公告)日：2018-03-29

申请号：US15588976

申请日：2017-05-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： QING CAO ,  SHU-JEN HAN ,  NING LI ,  JIANSHI TANG

IPC: H01L21/28 ,  H01L29/40 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L21/2807 ,  B82Y10/00 ,  H01L21/26513 ,  H01L21/28088 ,  H01L21/32056 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/775 ,  H01L29/78

Abstract: A method of forming a semiconductor device includes forming a channel layer on a substrate. A gate dielectric is deposited on the channel layer, and a mask is patterned on the gate dielectric. An exposed portion of the gate dielectric is removed to expose a first source/drain region and a second source/drain region of the channel layer. A first source/drain contact is formed on the first source/drain region and a second source/drain contact is formed on the second source/drain region. A cap layer is formed over the first source/drain contact and the second source/drain contact, and the mask is removed. Spacers are formed adjacent to sidewalls of the first source/drain contact and the second source/drain contact. An oxide region is formed in the cap layer and a carbon material is deposited on an exposed portion of the gate dielectric.

公开(公告)号：US20200328323A1

公开(公告)日：2020-10-15

申请号：US16381511

申请日：2019-04-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： JIANSHI TANG ,  NING LI ,  QING CAO

IPC: H01L31/18 ,  H04B10/11 ,  H01L33/00 ,  H01L31/0232 ,  H01L33/58

Abstract: A method and an apparatus are provided. The apparatus includes a three-dimensional semiconductor structure having a spherical array of fixed-position optoelectronic devices arranged over a relaxed elastomer by a controlled unbuckling process that orients the fixed-position optoelectronic devices to face in different directions in the spherical array to communicate in the different directions without motion of the apparatus and the fixed-position optoelectronic devices of the apparatus.

公开(公告)号：US20180350603A1

公开(公告)日：2018-12-06

申请号：US16042405

申请日：2018-07-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： QING CAO ,  SHU-JEN HAN ,  NING LI ,  JIANSHI TANG

IPC: H01L21/28 ,  H01L29/49 ,  H01L29/78 ,  H01L29/08 ,  H01L21/265 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L21/2807 ,  B82Y10/00 ,  H01L21/26513 ,  H01L21/28088 ,  H01L21/32056 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/775 ,  H01L29/78

Abstract: A method of forming a semiconductor device includes forming a channel layer on a substrate. A gate dielectric is deposited on the channel layer, and a mask is patterned on the gate dielectric. An exposed portion of the gate dielectric is removed to expose a first source/drain region and a second source/drain region of the channel layer. A first source/drain contact is formed on the first source/drain region and a second source/drain contact is formed on the second source/drain region. A cap layer is formed over the first source/drain contact and the second source/drain contact, and the mask is removed. Spacers are formed adjacent to sidewalls of the first source/drain contact and the second source/drain contact. An oxide region is formed in the cap layer and a carbon material is deposited on an exposed portion of the gate dielectric.