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公开(公告)号：US11310921B2
公开(公告)日：2022-04-19
申请号：US16660861
申请日：2019-10-23
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Kyle Indukummar Giesen , Matteo Cocchini , Sylvain Pharand
Abstract: A method may include forming a plurality of multilayer cores wherein each multilayer core comprises a sheet of cured dielectric material having a layer of metal on each side of the sheet of cured dielectric material, patterning each layer of metal in the plurality of multilayer cores to form wiring traces in each layer of metal, embedding a solder element in at least one sheet of a plurality of sheets of uncured dielectric material, wherein the solder element having a melting point temperature within a temperature range of a curing temperature of the uncured dielectric material, forming a printed circuit board by alternately stacking the plurality of multilayer cores with the plurality of sheets of uncured dielectric material between each multilayer core, laminating the stack of multilayer cores and sheets of uncured dielectric material to cause curing of the sheets of uncured dielectric material and melting of the solder element.
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公开(公告)号：US11209598B2
公开(公告)日：2021-12-28
申请号：US16288946
申请日：2019-02-28
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Barnim Alexander Janta-Polczynski , Isabel De Sousa , Jean Audet , Maryse Cournoyer , Sylvain Pharand , Roxan Lemire , Louis-Marie Achard , Paul Francis Fortier
IPC: G02B6/30
Abstract: A photonic package is provided. The photonic package includes a base substrate defining an aperture, a top die and a photonic integrated circuit (PIC) die. The top die includes a body with first and second top die sections. The first top die section is connectable with the base substrate. The PIC die includes body with first and second PIC die sections. The PIC die is disposable in the aperture such that the second PIC die section is connectable with the second top die section and the first PIC die section extends beyond the second top die section and is exposed for connection to a waveguide assembly.
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公开(公告)号：US20200185156A1
公开(公告)日：2020-06-11
申请号：US16211345
申请日：2018-12-06
Applicant: International Business Machines Corporation
Inventor： Charles L. Arvin , Sylvain Pharand , Bhupender Singh , Brian W. Quinlan
Abstract: A device including a substrate, an upper capacitor, and a lower capacitor is described. The upper capacitor is mounted on the substrate and includes an upper body and a pillar that extends from the upper body towards the substrate. The lower capacitor includes a lower body that is disposed both lateral to the pillar and at least in part between the upper body and the substrate. Each of the upper capacitor and the lower capacitor is a respective discrete circuit component. Such capacitor stacking configurations facilitate the placement of larger numbers of capacitors in close proximity to microprocessor cores in integrated circuit modules without the need to increase module size.
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4.发明申请公开(公告)号：US20150061158A1
公开(公告)日：2015-03-05
申请号：US14013182
申请日：2013-08-29
Applicant: International Business Machines Corporation
Inventor： Sylvain Pharand
IPC: H01L23/00
CPC classification number: H01L24/17 , H01L24/11 , H01L24/13 , H01L24/14 , H01L2224/0401 , H01L2224/05568 , H01L2224/1132 , H01L2224/11334 , H01L2224/1134 , H01L2224/11849 , H01L2224/11901 , H01L2224/13006 , H01L2224/13111 , H01L2224/13139 , H01L2224/14505 , H01L2224/16113 , H01L2224/16225 , H01L2224/16227 , H01L2224/16238 , H01L2224/17505 , H01L2224/17515 , H01L2224/81191 , H01L2224/81815 , H01L2924/01029 , H01L2924/01047 , H01L2924/0105 , H01L2924/014 , H01L2924/00014 , H01L2224/32 , H01L2924/00012
Abstract: A method including forming a first solder bump on a chip, the first solder bump made of a first alloy, and forming a second solder bump on a chip, the second solder bump made of a second alloy, where the first alloy has a different alloy concentration and is different from the second alloy.
Abstract translation: 一种包括在芯片上形成第一焊料凸块的方法，由第一合金制成的第一焊料凸块，以及在芯片上形成第二焊料凸点，所述第二焊料凸块由第二合金制成，其中所述第一合金具有不同的合金 浓度不同于第二种合金。
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公开(公告)号：US20220308564A1
公开(公告)日：2022-09-29
申请号：US17209574
申请日：2021-03-23
Applicant: International Business Machines Corporation
Inventor： Kirk D. Peterson , Steven Paul Ostrander , Stephanie E Allard , Charles L. Reynolds , Sungjun Chun , Daniel M. Dreps , Brian W. Quinlan , Sylvain Pharand , Jon Alfred Casey , David Edward Turnbull , Pascale Gagnon , Jean Labonte , Jean-Francois Bachand , Denis Blanchard
IPC: G05B19/418
Abstract: Multicomponent module assembly by identifying a failed site on a laminate comprising a plurality of sites, adding a machine discernible mark associated with the failed site, placing an electrically good element at a successful site; and providing an MCM comprising the laminate, and the electrically good element.
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Patent Agency Ranking
公开(公告)号：US20210127502A1
公开(公告)日：2021-04-29
申请号：US16660861
申请日：2019-10-23
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Kyle Indukummar Giesen , Matteo Cocchini , Sylvain Pharand
Abstract: A method may include forming a plurality of multilayer cores wherein each multilayer core comprises a sheet of cured dielectric material having a layer of metal on each side of the sheet of cured dielectric material, patterning each layer of metal in the plurality of multilayer cores to form wiring traces in each layer of metal, embedding a solder element in at least one sheet of a plurality of sheets of uncured dielectric material, wherein the solder element having a melting point temperature within a temperature range of a curing temperature of the uncured dielectric material, forming a printed circuit board by alternately stacking the plurality of multilayer cores with the plurality of sheets of uncured dielectric material between each multilayer core, laminating the stack of multilayer cores and sheets of uncured dielectric material to cause curing of the sheets of uncured dielectric material and melting of the solder element.
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公开(公告)号：US09793232B1
公开(公告)日：2017-10-17
申请号：US14988077
申请日：2016-01-05
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Charles L. Arvin , Luc Guerin , Sylvain Ouimet , Sylvain Pharand , Thomas A. Wassick
CPC classification number: H01L24/13 , C22C9/06 , H01L24/05 , H01L24/81 , H01L2224/0401 , H01L2224/05147 , H01L2224/10152 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/81815
Abstract: A standoff structure for providing improved interconnects is provided, wherein the structure employs nickel copper alloy or copper structures having increased resistivity.
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8.发明授权Joining a chip to a substrate with solder alloys having different reflow temperatures 有权使用具有不同回流温度的焊料合金将芯片连接到基板公开(公告)号：US09111793B2
公开(公告)日：2015-08-18
申请号：US14013182
申请日：2013-08-29
Applicant: International Business Machines Corporation
Inventor： Sylvain Pharand
IPC: H01L23/00
CPC classification number: H01L24/17 , H01L24/11 , H01L24/13 , H01L24/14 , H01L2224/0401 , H01L2224/05568 , H01L2224/1132 , H01L2224/11334 , H01L2224/1134 , H01L2224/11849 , H01L2224/11901 , H01L2224/13006 , H01L2224/13111 , H01L2224/13139 , H01L2224/14505 , H01L2224/16113 , H01L2224/16225 , H01L2224/16227 , H01L2224/16238 , H01L2224/17505 , H01L2224/17515 , H01L2224/81191 , H01L2224/81815 , H01L2924/01029 , H01L2924/01047 , H01L2924/0105 , H01L2924/014 , H01L2924/00014 , H01L2224/32 , H01L2924/00012
Abstract: A method including identifying a first connection location on a chip having a first connection type and a second connection location on the chip having a second connection type, applying a first solder alloy to the first connection location, heating the first solder alloy to a temperature sufficient to cause the first solder alloy to reflow, applying a second solder alloy to the second connection location, and heating the second solder alloy to a temperature sufficient to cause the second solder alloy to reflow.
Abstract translation: 一种方法，包括：在具有第二连接类型的芯片上识别具有第一连接类型和第二连接位置的芯片上的第一连接位置，将第一焊料合金施加到第一连接位置，将第一焊料合金加热到足够的温度 使第一焊料合金回流，向第二连接位置施加第二焊料合金，并将第二焊料合金加热至足以引起第二焊料合金回流的温度。
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公开(公告)号：US11004614B2
公开(公告)日：2021-05-11
申请号：US16211345
申请日：2018-12-06
Applicant: International Business Machines Corporation
Inventor： Charles L. Arvin , Sylvain Pharand , Bhupender Singh , Brian W. Quinlan
Abstract: A device including a substrate, an upper capacitor, and a lower capacitor is described. The upper capacitor is mounted on the substrate and includes an upper body and a pillar that extends from the upper body towards the substrate. The lower capacitor includes a lower body that is disposed both lateral to the pillar and at least in part between the upper body and the substrate. Each of the upper capacitor and the lower capacitor is a respective discrete circuit component. Such capacitor stacking configurations facilitate the placement of larger numbers of capacitors in close proximity to microprocessor cores in integrated circuit modules without the need to increase module size.
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公开(公告)号：US20200279840A1
公开(公告)日：2020-09-03
申请号：US16288946
申请日：2019-02-28
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： BARNIM ALEXANDER JANTA-POLCZYNSKI , Isabel De Sousa , Jean Audet , Maryse Cournoyer , Sylvain Pharand , Roxan Lemire , Louis-Marie Achard , Paul Francis Fortier
Abstract: A photonic package is provided. The photonic package includes a base substrate defining an aperture, a top die and a photonic integrated circuit (PIC) die. The top die includes a body with first and second top die sections. The first top die section is connectable with the base substrate. The PIC die includes body with first and second PIC die sections. The PIC die is disposable in the aperture such that the second PIC die section is connectable with the second top die section and the first PIC die section extends beyond the second top die section and is exposed for connection to a waveguide assembly.
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