公开(公告)号：US09515035B2

公开(公告)日：2016-12-06

申请号：US14577230

申请日：2014-12-19

Applicant: International Business Machines Corporation

Inventor： Timothy D. Sullivan ,  Thomas A. Wassick

IPC: H01L23/00 ,  H01L21/66 ,  H01L21/768 ,  H01L23/498

CPC classification number: H01L23/49838 ,  G06F17/5077 ,  H01L21/76898 ,  H01L22/14 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/647 ,  H01L24/10 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/1413 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Wiring structures, methods for providing a wiring structure, and methods for distributing currents with a wiring structure from one or more through-substrate vias to multiple bumps. A first current is directed from a first through-substrate via of a first electrical resistance through a first connection line to a first bump and directing a second current from the first through-substrate via through a second connection line of a second electrical resistance to a second bump. The first connection line has a first length relative to a first position of the first bump and a first cross-sectional area, the second connection line has a second length relative to a first position of the second bump and a second cross-sectional area, the second length is different from the first length, and the second cross-sectional area is different from the first cross-sectional area.

Abstract translation: 布线结构，用于提供布线结构的方法以及用布线结构从一个或多个贯穿基板通孔分配到多个凸起的方法。 第一电流从第一通过基板通过第一电阻通过第一连接线引导到第一凸起并且引导来自第一穿通基板的第二电流通过第二电阻的第二连接线到 第二次碰撞 第一连接线具有相对于第一凸块的第一位置的第一长度和第一横截面积，第二连接线相对于第二凸块的第一位置具有第二长度和第二横截面积， 第二长度与第一长度不同，第二横截面积与第一横截面积不同。

公开(公告)号：US08674506B2

公开(公告)日：2014-03-18

申请号：US13873801

申请日：2013-04-30

Applicant: International Business Machines Corporation

Inventor： Raschid J. Bezama ,  Timothy H. Daubenspeck ,  Gary LaFontant ,  Ian D. Melville ,  Ekta Misra ,  George J. Scott ,  Krystyna W. Semkow ,  Timothy D. Sullivan ,  Robin A. Susko ,  Thomas A. Wassick ,  Xiaojin Wei ,  Steven L. Wright

IPC: H01L23/498

CPC classification number: H01L23/49816 ,  H01L21/76804 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05011 ,  H01L2224/05012 ,  H01L2224/05013 ,  H01L2224/05094 ,  H01L2224/05551 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Structures and methods to reduce maximum current density in a solder ball are disclosed. A method includes forming a contact pad in a last wiring level and forming a plurality of wires of the contact pad extending from side edges of the contact pad to respective ones of a plurality of vias. Each one of the plurality of wires has substantially the same electrical resistance.

Abstract translation: 公开了减少焊球中的最大电流密度的结构和方法。 一种方法包括在最后的布线层中形成接触焊盘，并且形成从接触焊盘的侧边缘延伸到多个通孔中的多个通孔的接触焊盘的多个导线。 多个导线中的每一根具有基本上相同的电阻。

公开(公告)号：US10985129B2

公开(公告)日：2021-04-20

申请号：US16384148

申请日：2019-04-15

Applicant: International Business Machines Corporation

Inventor： Thomas E. Lombardi ,  Steve Ostrander ,  Krishna R. Tunga ,  Thomas A. Wassick

IPC: H01L23/00 ,  H01L23/36 ,  H01L21/48

Abstract: Multiple integrated circuit (IC) devices are connected to a top side metallization surface of a multi IC device carrier. The carrier includes resin based substrate layers and associated wiring line layers. To reduce stain of the resin layers, especially in region(s) within the carrier between the IC devices, a stiffener or stiffeners are applied to the back side metallization (BSM) surface of the IC device carrier. The stiffener(s) reduce the amount of curvature of the IC device carrier and reduce the strain seen by the resin layer(s), thereby mitigating the risk for cracks forming and expanding within the resin layers.

公开(公告)号：US20200328177A1

公开(公告)日：2020-10-15

申请号：US16384148

申请日：2019-04-15

Applicant: International Business Machines Corporation

Inventor： Thomas E. Lombardi ,  Steve Ostrander ,  Krishna R. Tunga ,  Thomas A. Wassick

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/36

Abstract: Multiple integrated circuit (IC) devices are connected to a top side metallization surface of a multi IC device carrier. The carrier includes resin based substrate layers and associated wiring line layers. To reduce stain of the resin layers, especially in region(s) within the carrier between the IC devices, a stiffener or stiffeners are applied to the back side metallization (BSM) surface of the IC device carrier. The stiffener(s) reduce the amount of curvature of the IC device carrier and reduce the strain seen by the resin layer(s), thereby mitigating the risk for cracks forming and expanding within the resin layers.

公开(公告)号：US10381276B2

公开(公告)日：2019-08-13

申请号：US14973165

申请日：2015-12-17

Applicant: International Business Machines Corporation

Inventor： Sushumna Iruvanti ,  Shidong Li ,  Marek A. Orlowski ,  David L. Questad ,  Tuhin Sinha ,  Krishna R. Tunga ,  Thomas A. Wassick ,  Randall J. Werner ,  Jeffrey A. Zitz

IPC: H01L21/48 ,  G06F17/50 ,  H01L21/66 ,  H01L23/498

Abstract: A laminate includes a plurality of buildup layers disposed on a core and a plurality of unit cells defined in the buildup layers. Each unit cell includes: at least one test via that passes through at least two of the buildup layers and that is electrically connected to testing locations on a probe accessible location of the laminate; and two or more dummy vias disposed in the unit cell. The dummy vias are arranged in the unit cell at one of a plurality of distances from the test via.

公开(公告)号：US10249548B2

公开(公告)日：2019-04-02

申请号：US15813536

申请日：2017-11-15

Applicant: International Business Machines Corporation

Inventor： Sushumna Iruvanti ,  Shidong Li ,  Marek A. Orlowski ,  David L. Questad ,  Tuhin Sinha ,  Krishna R. Tunga ,  Thomas A. Wassick ,  Randall J. Werner ,  Jeffrey A. Zitz

IPC: H01L21/00 ,  H01L21/66 ,  G06F17/50 ,  H01L23/498 ,  H01L21/48

Abstract: A laminate includes a plurality of buildup layers disposed on a core and a plurality of unit cells defined in the buildup layers. Each unit cell includes: at least one test via that passes through at least two of the buildup layers and that is electrically connected to testing locations on a probe accessible location of the laminate; and two or more dummy vias disposed in the unit cell. The dummy vias are arranged in the unit cell at one of a plurality of distances from the test via.

公开(公告)号：US09793232B1

公开(公告)日：2017-10-17

申请号：US14988077

申请日：2016-01-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Charles L. Arvin ,  Luc Guerin ,  Sylvain Ouimet ,  Sylvain Pharand ,  Thomas A. Wassick

IPC: H01L21/44 ,  H01L23/00 ,  C22C9/06

CPC classification number: H01L24/13 ,  C22C9/06 ,  H01L24/05 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/10152 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/81815

Abstract: A standoff structure for providing improved interconnects is provided, wherein the structure employs nickel copper alloy or copper structures having increased resistivity.

公开(公告)号：US09190376B1

公开(公告)日：2015-11-17

申请号：US14277832

申请日：2014-05-15

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Brian M. Erwin ,  Eric D. Perfecto ,  Wolfgang Sauter ,  Thomas A. Wassick

IPC: H01L23/48 ,  H01L23/00

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L2224/03912 ,  H01L2224/05023 ,  H01L2224/05568 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/10145 ,  H01L2224/1132 ,  H01L2224/11332 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/13017 ,  H01L2224/13083 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13565 ,  H01L2224/13582 ,  H01L2224/1369 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: The present invention relates generally to and more particularly, to a method of fabricating a pillar interconnect structure with non-wettable sidewalls and the resulting structure. More specifically, the present invention may include exposing only the sidewalls of a pillar to an organic material that reacts with metal of the pillar to form an organo-metallic layer on sidewalls of the pillar. The organo-metallic layer may prevent solder from wetting on the sidewalls of the pillar during subsequent bonding/reflow processes.

Abstract translation: 本发明一般而且更具体地涉及制造具有不可润湿侧壁的柱状互连结构的方法以及所得到的结构。 更具体地说，本发明可以包括将柱的侧壁仅暴露于与柱的金属反应的有机材料，以在柱的侧壁上形成有机金属层。 在随后的接合/回流工艺期间，有机金属层可以防止焊料在柱的侧壁上润湿。

公开(公告)号：US11043468B2

公开(公告)日：2021-06-22

申请号：US16773368

申请日：2020-01-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Charles L. Arvin ,  Clement J. Fortin ,  Christopher D. Muzzy ,  Thomas A. Wassick

IPC: H01L23/00 ,  H01L23/498

Abstract: A method and structure for joining a semiconductor device and a laminate substrate or two laminate substrates where the joint is formed with lead free solders and lead free compositions. The various lead free solders and lead free compositions are chosen so that there is a sufficient difference in liquidus temperatures such that some components may be joined to, or removed from, the laminate substrate without disturbing other components on the laminate substrate.

公开(公告)号：US10586782B2

公开(公告)日：2020-03-10

申请号：US15640475

申请日：2017-07-01

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Clement J. Fortin ,  Christopher D. Muzzy ,  Brian W. Quinlan ,  Thomas A. Wassick ,  Thomas Weiss

IPC: H01L23/00 ,  H01L23/498

Abstract: A method and structure for joining a semiconductor device and a laminate substrate or two laminate substrates where the joint is formed with lead free solders and lead free compositions. The various lead free solders and lead free compositions are chosen so that there is a sufficient difference in liquidus temperatures such that some components may be joined to, or removed from, the laminate substrate without disturbing other components on the laminate substrate.