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公开(公告)号：US09537015B2
公开(公告)日：2017-01-03
申请号：US14974763
申请日：2015-12-18
IPC分类号： H01L29/78 , H01L29/786 , H01L29/66 , H01L29/417 , H01L29/423 , H01L21/324 , H01L29/06
CPC分类号： H01L29/78696 , H01L21/30604 , H01L21/3247 , H01L21/823425 , H01L21/823431 , H01L29/0673 , H01L29/0676 , H01L29/1037 , H01L29/41733 , H01L29/41791 , H01L29/42384 , H01L29/42392 , H01L29/66795 , H01L29/66818 , H01L29/7831 , H01L29/785 , H01L29/7854 , H01L29/7856
摘要： Transistors including one or more semiconductor fins formed on a substrate. The one or more semiconductor fins are thinner in a channel region than in source and drain regions and have rounded corners formed by an anneal in a gaseous environment. A gate dielectric layer is on the channel region of the one or more semiconductor fins, conforming to the contours of the one or more semiconductor fins. A gate structure is on the gate dielectric layer.
摘要翻译： 晶体管包括形成在基板上的一个或多个半导体鳍片。 一个或多个半导体鳍片在沟道区域比在源极和漏极区域更薄，并且具有通过在气体环境中的退火形成的圆角。 栅介质层位于一个或多个半导体鳍片的沟道区上，符合一个或多个半导体鳍片的轮廓。 栅极结构在栅极电介质层上。
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公开(公告)号：US10020303B2
公开(公告)日：2018-07-10
申请号：US14666464
申请日：2015-03-24
发明人： Hong He , Shogo Mochizuki , Chiahsun Tseng , Chun-Chen Yeh , Yunpeng Yin
IPC分类号： H01L21/8234 , H01L21/02 , H01L21/3105 , H01L27/088 , H01L29/04 , H01L29/66 , H01L29/78 , H01L29/06 , H01L21/306 , H01L29/08
CPC分类号： H01L27/0886 , H01L21/02271 , H01L21/0257 , H01L21/30604 , H01L21/823431 , H01L21/823437 , H01L21/823481 , H01L29/045 , H01L29/0649 , H01L29/0653 , H01L29/0847 , H01L29/66545 , H01L29/66795 , H01L29/6681 , H01L29/785 , H01L29/7851
摘要： Methods for forming semiconductor devices having non-merged fin extensions. Methods for forming semiconductor devices include forming trenches in an insulator layer of a substrate. Fins are formed in the trenches and a dummy gate is formed over the fins, leaving a source and drain region exposed. The fins are etched below a surface level of a surrounding insulator layer. Fin extensions are epitaxially grown from the etched fins.
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公开(公告)号：US09991258B2
公开(公告)日：2018-06-05
申请号：US15292768
申请日：2016-10-13
发明人： Hong He , Shogo Mochizuki , Chiahsun Tseng , Chun-Chen Yeh , Yunpeng Yin
IPC分类号： H01L29/06 , H01L29/04 , H01L29/08 , H01L27/088 , H01L29/66 , H01L29/78 , H01L21/02 , H01L21/306 , H01L21/8234
CPC分类号： H01L27/0886 , H01L21/02271 , H01L21/0257 , H01L21/30604 , H01L21/823431 , H01L21/823437 , H01L21/823481 , H01L29/045 , H01L29/0649 , H01L29/0653 , H01L29/0847 , H01L29/66545 , H01L29/66795 , H01L29/6681 , H01L29/785 , H01L29/7851
摘要： Semiconductor devices include multiple fins formed in trenches in an insulator layer. Each of the plurality of fins has a uniform crystal orientation and a fin cap in a source and drain region that extends vertically and laterally beyond the trench. The fin caps of the respective fins are separate from one another. A gate structure is formed over the fins that leaves the source and drain regions exposed. The insulator layer at least partially covers a sidewall of the gate structure.
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公开(公告)号：US09793272B2
公开(公告)日：2017-10-17
申请号：US15170299
申请日：2016-06-01
发明人： Dechao Guo , Shogo Mochizuki , Andreas Scholze , Chun-Chen Yeh
IPC分类号： H01L27/088 , H01L21/8234 , H01L29/66 , H01L29/78 , H01L29/08 , H01L29/165 , H01L21/225 , H01L21/324 , H01L29/267
CPC分类号： H01L29/0847 , H01L21/2252 , H01L21/324 , H01L21/823418 , H01L21/823431 , H01L21/823437 , H01L27/0886 , H01L29/08 , H01L29/0843 , H01L29/086 , H01L29/0869 , H01L29/0878 , H01L29/0886 , H01L29/165 , H01L29/267 , H01L29/66 , H01L29/66545 , H01L29/66636 , H01L29/66681 , H01L29/66795 , H01L29/7816 , H01L29/7833 , H01L29/7848 , H01L29/7851
摘要： A semiconductor device including a gate structure on a channel region portion of a fin structure, and at least one of an epitaxial source region and an epitaxial drain region on a source region portion and a drain region portion of the fin structure. At least one of the epitaxial source region portion and the epitaxial drain region portion include a first concentration doped portion adjacent to the fin structure, and a second concentration doped portion on the first concentration doped portion. The second concentration portion has a greater dopant concentration than the first concentration doped portion. An extension dopant region extending into the channel portion of the fin structure having an abrupt dopant concentration gradient of n-type or p-type dopants of 7 nm per decade or greater.
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5.发明授权公开(公告)号：US09786661B2
公开(公告)日：2017-10-10
申请号：US15170273
申请日：2016-06-01
发明人： Dechao Guo , Shogo Mochizuki , Andreas Scholze , Chun-Chen Yeh
IPC分类号： H01L27/088 , H01L21/8234 , H01L29/66 , H01L29/78 , H01L29/08 , H01L29/165 , H01L21/225 , H01L21/324 , H01L29/267
CPC分类号： H01L29/0847 , H01L21/2252 , H01L21/324 , H01L21/823418 , H01L21/823431 , H01L21/823437 , H01L27/0886 , H01L29/08 , H01L29/0843 , H01L29/086 , H01L29/0869 , H01L29/0878 , H01L29/0886 , H01L29/165 , H01L29/267 , H01L29/66 , H01L29/66545 , H01L29/66636 , H01L29/66681 , H01L29/66795 , H01L29/7816 , H01L29/7833 , H01L29/7848 , H01L29/7851
摘要： A semiconductor device including a gate structure on a channel region portion of a fin structure, and at least one of an epitaxial source region and an epitaxial drain region on a source region portion and a drain region portion of the fin structure. At least one of the epitaxial source region portion and the epitaxial drain region portion include a first concentration doped portion adjacent to the fin structure, and a second concentration doped portion on the first concentration doped portion. The second concentration portion has a greater dopant concentration than the first concentration doped portion. An extension dopant region extending into the channel portion of the fin structure having an abrupt dopant concentration gradient of n-type or p-type dopants of 7 nm per decade or greater.
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公开(公告)号：US09263554B2
公开(公告)日：2016-02-16
申请号：US13909602
申请日：2013-06-04
IPC分类号： H01L21/336 , H01L29/66 , H01L29/78
CPC分类号： H01L29/78696 , H01L21/30604 , H01L21/3247 , H01L21/823425 , H01L21/823431 , H01L29/0673 , H01L29/0676 , H01L29/1037 , H01L29/41733 , H01L29/41791 , H01L29/42384 , H01L29/42392 , H01L29/66795 , H01L29/66818 , H01L29/7831 , H01L29/785 , H01L29/7854 , H01L29/7856
摘要： Transistors and methods for fabricating the same include forming one or more semiconductor fins on a substrate; covering source and drain regions of the one or more semiconductor fins with a protective layer; annealing uncovered channel portions of the one or more semiconductor fins in a gaseous environment to reduce fin width and round corners of the one or more semiconductor fins; and forming a dielectric layer and gate over the thinned fins.
摘要翻译： 晶体管及其制造方法包括在基板上形成一个或多个半导体翅片; 用保护层覆盖一个或多个半导体翅片的源区和漏区; 在气态环境中退火所述一个或多个半导体翅片的未覆盖通道部分以减小所述一个或多个半导体翅片的翅片宽度和圆角; 并在薄的翅片上形成电介质层和栅极。
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公开(公告)号：US10312377B2
公开(公告)日：2019-06-04
申请号：US15291137
申请日：2016-10-12
IPC分类号： H01L29/78 , H01L29/786 , H01L29/66 , H01L29/417 , H01L29/423 , H01L21/324 , H01L29/06 , H01L21/306 , H01L21/8234 , H01L29/10
摘要： Transistors including one or more semiconductor fins formed on a substrate. The one or more semiconductor fins are thinner in a channel region than in source and drain regions and have rounded corners. There is a gate stack on the channel region of the one or more semiconductor fins.
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公开(公告)号：US09666726B2
公开(公告)日：2017-05-30
申请号：US14949430
申请日：2015-11-23
IPC分类号： H01L21/324 , H01L29/66 , H01L29/786 , H01L29/78 , H01L29/417 , H01L29/423 , H01L29/06
CPC分类号： H01L29/78696 , H01L21/30604 , H01L21/3247 , H01L21/823425 , H01L21/823431 , H01L29/0673 , H01L29/0676 , H01L29/1037 , H01L29/41733 , H01L29/41791 , H01L29/42384 , H01L29/42392 , H01L29/66795 , H01L29/66818 , H01L29/7831 , H01L29/785 , H01L29/7854 , H01L29/7856
摘要： Transistors and methods for fabricating the same include annealing channel portions of one or more semiconductor fins that are uncovered by a protective layer in a gaseous environment to reduce fin width, to produce a fin profile that is widest at the bottom and tapers toward the top, and to round corners of the one or more semiconductor fins.
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公开(公告)号：US09105663B1
公开(公告)日：2015-08-11
申请号：US14168175
申请日：2014-01-30
申请人： International Business Machines Corporation , Renesas Electronics Corporation , STMicroelectronics, Inc.
发明人： Kangguo Cheng , Ali Khakifirooz , Nicolas Loubet , Shogo Mochizuki , Alexander Reznicek , Raghavasimhan Sreenivasan , Chun-Chen Yeh
IPC分类号： H01L27/12 , H01L29/66 , H01L21/225 , H01L29/78
CPC分类号： H01L29/66795 , H01L21/2254 , H01L21/30604 , H01L21/3065 , H01L29/7841 , H01L29/7848 , H01L29/785
摘要： The present disclosure generally provides for a method of forming a FinFET with a silicon germanium (SiGe) stressor, in addition to a FinFET structure obtained from embodiments of the method. The method can include forming a semiconductor fin on a buried insulator layer; forming a gate structure on the semiconductor fin; forming a silicon germanium (SiGe) layer on the buried insulator layer, wherein the SiGe layer contacts the semiconductor fin; and heating the SiGe layer, wherein the heating diffuses germanium (Ge) into the semiconductor fin.
摘要翻译： 本公开通常提供了除了由该方法的实施例获得的FinFET结构之外还形成具有硅锗（SiGe）应力源的FinFET的方法。 该方法可以包括在掩埋绝缘体层上形成半导体鳍片; 在半导体鳍片上形成栅极结构; 在所述掩埋绝缘体层上形成硅锗层（SiGe），其中所述SiGe层接触所述半导体鳍片; 并加热SiGe层，其中加热使锗（Ge）扩散到半导体鳍片中。
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10.发明授权公开(公告)号：US10249714B2
公开(公告)日：2019-04-02
申请号：US15634411
申请日：2017-06-27
发明人： Dechao Guo , Shogo Mochizuki , Andreas Scholze , Chun-Chen Yeh
IPC分类号： H01L29/08 , H01L21/8234 , H01L29/66 , H01L29/78 , H01L29/165 , H01L21/225 , H01L21/324 , H01L27/088 , H01L29/267
摘要： A semiconductor device including a gate structure on a channel region portion of a fin structure, and at least one of an epitaxial source region and an epitaxial drain region on a source region portion and a drain region portion of the fin structure. At least one of the epitaxial source region portion and the epitaxial drain region portion include a first concentration doped portion adjacent to the fin structure, and a second concentration doped portion on the first concentration doped portion. The second concentration portion has a greater dopant concentration than the first concentration doped portion. An extension dopant region extending into the channel portion of the fin structure having an abrupt dopant concentration gradient of n-type or p-type dopants of 7 nm per decade or greater.
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