公开(公告)号：US09269655B2

公开(公告)日：2016-02-23

申请号：US14825382

申请日：2015-08-13

申请人： International Rectifier Corporation

发明人： Eung San Cho ,  Andrew N. Sawle ,  Mark Pavier ,  Daniel Cutler

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/495 ,  H01L25/00 ,  H01L25/07 ,  H01L23/00

CPC分类号： H01L21/84 ,  H01L21/4825 ,  H01L21/4871 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49575 ,  H01L24/16 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L25/072 ,  H01L25/117 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16245 ,  H01L2224/24137 ,  H01L2224/24245 ,  H01L2224/29101 ,  H01L2224/2929 ,  H01L2224/32245 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/8382 ,  H01L2224/8384 ,  H01L2224/92224 ,  H01L2224/92244 ,  H01L2924/10253 ,  H01L2924/10323 ,  H01L2924/10325 ,  H01L2924/1033 ,  H01L2924/10334 ,  H01L2924/10341 ,  H01L2924/10344 ,  H01L2924/10346 ,  H01L2924/10355 ,  H01L2924/10356 ,  H01L2924/10357 ,  H01L2924/10358 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1426 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/014

摘要： In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage having a control drain attached to the die side of the control conductive carrier. The control conductive carrier is configured to sink heat produced by the control FET into the mounting surface. The semiconductor package includes a sync conductive carrier having another die side and another opposite I/O side connecting the semiconductor package to the mounting surface, and a sync FET of the power converter switching stage having a sync source attached to the die side of the sync conductive carrier.

摘要翻译： 在一个实施方案中，半导体封装包括具有裸片侧的控制导电载体和将半导体封装连接到安装表面的相反的输入/输出（I / O）侧。 半导体封装还包括功率转换器开关级的控制FET，其具有附着到控制导电载体的管芯侧的控制漏极。 控制导电载体被配置为将由控制FET产生的热量吸收到安装表面中。 半导体封装包括具有另一管芯侧的同步导电载体和将半导体封装连接到安装表面的另一个相反的I / O侧，以及功率转换器开关级的同步FET，其具有连接到同步的管芯侧的同步源 导电载体。

公开(公告)号：US20150348888A1

公开(公告)日：2015-12-03

申请号：US14825509

申请日：2015-08-13

申请人： International Rectifier Corporation

发明人： Eung San Cho ,  Andrew N. Sawle ,  Mark Pavier ,  Daniel Cutler

IPC分类号： H01L23/495 ,  H01L25/18 ,  H01L23/00 ,  H01L25/07

CPC分类号： H01L21/84 ,  H01L21/4825 ,  H01L21/4871 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49575 ,  H01L24/16 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L25/072 ,  H01L25/117 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/16245 ,  H01L2224/24137 ,  H01L2224/24245 ,  H01L2224/29101 ,  H01L2224/2929 ,  H01L2224/32245 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/8382 ,  H01L2224/8384 ,  H01L2224/92224 ,  H01L2224/92244 ,  H01L2924/10253 ,  H01L2924/10323 ,  H01L2924/10325 ,  H01L2924/1033 ,  H01L2924/10334 ,  H01L2924/10341 ,  H01L2924/10344 ,  H01L2924/10346 ,  H01L2924/10355 ,  H01L2924/10356 ,  H01L2924/10357 ,  H01L2924/10358 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1426 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/014

摘要： In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage having a control drain attached to the die side of the control conductive carrier. The control conductive carrier is configured to sink heat produced by the control FET into the mounting surface. The semiconductor package includes a sync conductive carrier having another die side and another opposite I/O side connecting the semiconductor package to the mounting surface, and a sync FET of the power converter switching stage having a sync source attached to the die side of the sync conductive carrier.

摘要翻译： 在一个实施方案中，半导体封装包括具有裸片侧的控制导电载体和将半导体封装连接到安装表面的相反的输入/输出（I / O）侧。 半导体封装还包括功率转换器开关级的控制FET，其具有附着到控制导电载体的管芯侧的控制漏极。 控制导电载体被配置为将由控制FET产生的热量吸收到安装表面中。 半导体封装包括具有另一管芯侧的同步导电载体和将半导体封装连接到安装表面的另一个相反的I / O侧，以及功率转换器开关级的同步FET，其具有连接到同步的管芯侧的同步源 导电载体。

公开(公告)号：US20140103393A1

公开(公告)日：2014-04-17

申请号：US14018238

申请日：2013-09-04

申请人： INTERNATIONAL RECTIFIER CORPORATION

发明人： Mark Pavier ,  Daniel Cutler ,  Scott Palmer ,  Clive O'Dell ,  Rupert Burbidge

IPC分类号： H01L29/739 ,  H01L23/498

CPC分类号： H01L23/522 ,  H01L23/49811 ,  H01L25/072 ,  H01L25/18 ,  H01L27/0647 ,  H01L29/7393 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to an exemplary implementation, a power component includes a component substrate and a power semiconductor device electrically and mechanically coupled to the component substrate. The power component also includes at least one first peripheral contact and at least one second peripheral contact situated on the component substrate. A power semiconductor device is situated between the at least one first peripheral contact and the at least one second peripheral contact. The at least one first peripheral contact, the at least one second peripheral contact, and a surface electrode of the power semiconductor device are configured for surface mounting. The at least one first peripheral contact can be electrically coupled to the power semiconductor device.

摘要翻译： 根据示例性实施方式，功率部件包括电气和机械耦合到部件基板的部件基板和功率半导体器件。 功率部件还包括位于组件衬底上的至少一个第一外围接触件和至少一个第二外围触头。 功率半导体器件位于至少一个第一外围接触件和至少一个第二外围接触件之间。 功率半导体器件的至少一个第一周边接触件，至少一个第二外围接触件和表面电极被配置为用于表面安装。 所述至少一个第一外围接触件可电耦合到功率半导体器件。

公开(公告)号：US09362221B2

公开(公告)日：2016-06-07

申请号：US14688344

申请日：2015-04-16

申请人： International Rectifier Corporation

发明人： Mark Pavier ,  Daniel Cutler ,  Scott Palmer ,  Clive O'Dell ,  Rupert Burbidge

IPC分类号： H01L25/00 ,  H01L27/00 ,  H01L23/522 ,  H01L29/739 ,  H01L23/498 ,  H01L25/07 ,  H01L27/06

CPC分类号： H01L23/522 ,  H01L23/49811 ,  H01L25/072 ,  H01L25/18 ,  H01L27/0647 ,  H01L29/7393 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to an exemplary implementation, a power component includes a component substrate and a power semiconductor device electrically and mechanically coupled to the component substrate. The power component also includes at least one first peripheral contact and at least one second peripheral contact situated on the component substrate. A power semiconductor device is situated between the at least one first peripheral contact and the at least one second peripheral contact. The at least one first peripheral contact, the at least one second peripheral contact, and a surface electrode of the power semiconductor device are configured for surface mounting. The at least one first peripheral contact can be electrically coupled to the power semiconductor device.

公开(公告)号：US09111921B2

公开(公告)日：2015-08-18

申请号：US14022584

申请日：2013-09-10

申请人： International Rectifier Corporation

发明人： Eung San Cho ,  Andrew N. Sawle ,  Mark Pavier ,  Daniel Cutler

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L23/495 ,  H01L25/07 ,  H01L25/11 ,  H01L21/48 ,  H01L25/16 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

CPC分类号： H01L21/84 ,  H01L21/4825 ,  H01L21/4871 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49575 ,  H01L24/16 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L25/072 ,  H01L25/117 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16245 ,  H01L2224/24137 ,  H01L2224/24245 ,  H01L2224/29101 ,  H01L2224/2929 ,  H01L2224/32245 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/8382 ,  H01L2224/8384 ,  H01L2224/92224 ,  H01L2224/92244 ,  H01L2924/10253 ,  H01L2924/10323 ,  H01L2924/10325 ,  H01L2924/1033 ,  H01L2924/10334 ,  H01L2924/10341 ,  H01L2924/10344 ,  H01L2924/10346 ,  H01L2924/10355 ,  H01L2924/10356 ,  H01L2924/10357 ,  H01L2924/10358 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1426 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/014

摘要： In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage having a control drain attached to the die side of the control conductive carrier. The control conductive carrier is configured to sink heat produced by the control FET into the mounting surface. The semiconductor package includes a sync conductive carrier having another die side and another opposite I/O side connecting the semiconductor package to the mounting surface, and a sync FET of the power converter switching stage having a sync source attached to the die side of the sync conductive carrier.

摘要翻译： 在一个实施方案中，半导体封装包括具有裸片侧的控制导电载体和将半导体封装连接到安装表面的相反的输入/输出（I / O）侧。 半导体封装还包括功率转换器开关级的控制FET，其具有附着到控制导电载体的管芯侧的控制漏极。 控制导电载体被配置为将由控制FET产生的热量吸收到安装表面中。 半导体封装包括具有另一管芯侧的同步导电载体和将半导体封装连接到安装表面的另一个相反的I / O侧，以及功率转换器开关级的同步FET，其具有连接到同步的管芯侧的同步源 导电载体。

公开(公告)号：US20140110788A1

公开(公告)日：2014-04-24

申请号：US14021802

申请日：2013-09-09

申请人： International Rectifier Corporation

发明人： Eung San Cho ,  Andrew N. Sawle ,  Mark Pavier ,  Daniel Cutler

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/7827 ,  H01L23/3107 ,  H01L23/36 ,  H01L23/492 ,  H01L23/49517 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/18 ,  H01L24/19 ,  H01L25/072 ,  H01L25/115 ,  H01L29/66666 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00

摘要： In one implementation, a semiconductor package includes a top-drain vertical FET in a first active die, a source of the top-drain vertical FET situated on a source side of the first active die and a drain and a gate of the top-drain vertical FET situated on a drain side of the first active die. The semiconductor package also includes a bottom-drain vertical FET in a second active die, a source and a gate of the bottom-drain vertical FET situated on a source side of the second active die and a drain of the bottom-drain vertical FET situated on a drain side of the second active die. The semiconductor package includes a conductive carrier attached to the source side of the first active die and to the drain side of the second active die, the conductive carrier coupling the source of the top-drain vertical FET to the drain of the bottom-drain vertical FET.

摘要翻译： 在一个实施方案中，半导体封装包括位于第一有源管芯中的顶排垂直FET，位于第一有源管芯的源极侧的顶排垂直FET的源极以及顶漏的栅极和漏极 位于第一有源管芯的漏极侧的垂直FET。 半导体封装还包括位于第二有源管芯中的底漏极垂直FET，位于第二有源管芯的源极侧的底漏垂直FET的源极和栅极以及位于底部漏极垂直FET的漏极 在第二有源管芯的漏极侧。 半导体封装包括附接到第一有源管芯的源极侧和第二有源管芯的漏极侧的导电载体，导电载体将顶部漏极垂直FET的源极耦合到底部漏极垂直的漏极 FET。

公开(公告)号：US09397212B2

公开(公告)日：2016-07-19

申请号：US14021802

申请日：2013-09-09

申请人： International Rectifier Corporation

发明人： Eung San Cho ,  Andrew N. Sawle ,  Mark Pavier ,  Daniel Cutler

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L23/492 ,  H01L23/495 ,  H01L25/07 ,  H01L25/11 ,  H01L23/36 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L29/7827 ,  H01L23/3107 ,  H01L23/36 ,  H01L23/492 ,  H01L23/49517 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/18 ,  H01L24/19 ,  H01L25/072 ,  H01L25/115 ,  H01L29/66666 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00

摘要： In one implementation, a semiconductor package includes a top-drain vertical FET in a first active die, a source of the top-drain vertical FET situated on a source side of the first active die and a drain and a gate of the top-drain vertical FET situated on a drain side of the first active die. The semiconductor package also includes a bottom-drain vertical FET in a second active die, a source and a gate of the bottom-drain vertical FET situated on a source side of the second active die and a drain of the bottom-drain vertical FET situated on a drain side of the second active die. The semiconductor package includes a conductive carrier attached to the source side of the first active die and to the drain side of the second active die, the conductive carrier coupling the source of the top-drain vertical FET to the drain of the bottom-drain vertical FET.

摘要翻译： 在一个实施方案中，半导体封装包括位于第一有源管芯中的顶排垂直FET，位于第一有源管芯的源极侧的顶排垂直FET的源极以及顶漏的栅极和漏极 位于第一有源管芯的漏极侧的垂直FET。 半导体封装还包括位于第二有源管芯中的底漏极垂直FET，位于第二有源管芯的源极侧的底漏垂直FET的源极和栅极以及位于底部漏极垂直FET的漏极 在第二有源管芯的漏极侧。 半导体封装包括附接到第一有源管芯的源极侧和第二有源管芯的漏极侧的导电载体，导电载体将顶部漏极垂直FET的源极耦合到底部漏极垂直的漏极 FET。

公开(公告)号：US09012990B2

公开(公告)日：2015-04-21

申请号：US14018238

申请日：2013-09-04

申请人： International Rectifier Corporation

发明人： Mark Pavier ,  Daniel Cutler ,  Scott Palmer ,  Clive O'Dell ,  Rupert Burbidge

IPC分类号： H01L29/66 ,  H01L29/739 ,  H01L23/498 ,  H01L25/07

CPC分类号： H01L23/522 ,  H01L23/49811 ,  H01L25/072 ,  H01L25/18 ,  H01L27/0647 ,  H01L29/7393 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to an exemplary implementation, a power component includes a component substrate and a power semiconductor device electrically and mechanically coupled to the component substrate. The power component also includes at least one first peripheral contact and at least one second peripheral contact situated on the component substrate. A power semiconductor device is situated between the at least one first peripheral contact and the at least one second peripheral contact. The at least one first peripheral contact, the at least one second peripheral contact, and a surface electrode of the power semiconductor device are configured for surface mounting. The at least one first peripheral contact can be electrically coupled to the power semiconductor device.

摘要翻译： 根据示例性实施方式，功率部件包括电气和机械耦合到部件基板的部件基板和功率半导体器件。 功率部件还包括位于组件衬底上的至少一个第一外周接触件和至少一个第二外围触头。 功率半导体器件位于至少一个第一外围接触件和至少一个第二外围接触件之间。 功率半导体器件的至少一个第一周边接触件，至少一个第二外围接触件和表面电极被配置用于表面安装。 所述至少一个第一外围接触件可电耦合到功率半导体器件。

公开(公告)号：US20140110796A1

公开(公告)日：2014-04-24

申请号：US14022584

申请日：2013-09-10

申请人： International Rectifier Corporation

发明人： Eung San Cho ,  Andrew N. Sawle ,  Mark Pavier ,  Daniel Cutler

IPC分类号： H01L23/495 ,  H01L21/48

CPC分类号： H01L21/84 ,  H01L21/4825 ,  H01L21/4871 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49575 ,  H01L24/16 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L25/072 ,  H01L25/117 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16245 ,  H01L2224/24137 ,  H01L2224/24245 ,  H01L2224/29101 ,  H01L2224/2929 ,  H01L2224/32245 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/8382 ,  H01L2224/8384 ,  H01L2224/92224 ,  H01L2224/92244 ,  H01L2924/10253 ,  H01L2924/10323 ,  H01L2924/10325 ,  H01L2924/1033 ,  H01L2924/10334 ,  H01L2924/10341 ,  H01L2924/10344 ,  H01L2924/10346 ,  H01L2924/10355 ,  H01L2924/10356 ,  H01L2924/10357 ,  H01L2924/10358 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1426 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/014

摘要： In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage having a control drain attached to the die side of the control conductive carrier. The control conductive carrier is configured to sink heat produced by the control FET into the mounting surface. The semiconductor package includes a sync conductive carrier having another die side and another opposite I/O side connecting the semiconductor package to the mounting surface, and a sync FET of the power converter switching stage having a sync source attached to the die side of the sync conductive carrier.

摘要翻译： 在一个实施方案中，半导体封装包括具有裸片侧的控制导电载体和将半导体封装连接到安装表面的相反的输入/输出（I / O）侧。 半导体封装还包括功率转换器开关级的控制FET，其具有附着到控制导电载体的管芯侧的控制漏极。 控制导电载体被配置为将由控制FET产生的热量吸收到安装表面中。 半导体封装包括具有另一管芯侧的同步导电载体和将半导体封装连接到安装表面的另一个相反的I / O侧，以及功率转换器开关级的同步FET，其具有连接到同步的管芯侧的同步源 导电载体。

公开(公告)号：US20150348887A1

公开(公告)日：2015-12-03

申请号：US14825382

申请日：2015-08-13

申请人： International Rectifier Corporation

发明人： Eung San Cho ,  Andrew N. Sawle ,  Mark Pavier ,  Daniel Cutler

IPC分类号： H01L23/495 ,  H01L25/07 ,  H01L23/00 ,  H01L25/00

CPC分类号： H01L21/84 ,  H01L21/4825 ,  H01L21/4871 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49575 ,  H01L24/16 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L25/072 ,  H01L25/117 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16245 ,  H01L2224/24137 ,  H01L2224/24245 ,  H01L2224/29101 ,  H01L2224/2929 ,  H01L2224/32245 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/8382 ,  H01L2224/8384 ,  H01L2224/92224 ,  H01L2224/92244 ,  H01L2924/10253 ,  H01L2924/10323 ,  H01L2924/10325 ,  H01L2924/1033 ,  H01L2924/10334 ,  H01L2924/10341 ,  H01L2924/10344 ,  H01L2924/10346 ,  H01L2924/10355 ,  H01L2924/10356 ,  H01L2924/10357 ,  H01L2924/10358 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1426 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/014

摘要： In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage having a control drain attached to the die side of the control conductive carrier. The control conductive carrier is configured to sink heat produced by the control FET into the mounting surface. The semiconductor package includes a sync conductive carrier having another die side and another opposite I/O side connecting the semiconductor package to the mounting surface, and a sync FET of the power converter switching stage having a sync source attached to the die side of the sync conductive carrier.

摘要翻译： 在一个实施方案中，半导体封装包括具有裸片侧的控制导电载体和将半导体封装连接到安装表面的相反的输入/输出（I / O）侧。 半导体封装还包括功率转换器开关级的控制FET，其具有附着到控制导电载体的管芯侧的控制漏极。 控制导电载体被配置为将由控制FET产生的热量吸收到安装表面中。 半导体封装包括具有另一管芯侧的同步导电载体和将半导体封装连接到安装表面的另一相对I / O侧，以及功率转换器开关级的同步FET，其具有连接到同步的管芯侧的同步源 导电载体。