Method of manufacturing integrated circuit packaging system with support structure
    4.
    发明授权
    Method of manufacturing integrated circuit packaging system with support structure 有权
    具有支撑结构的集成电路封装系统的制造方法

    公开(公告)号:US08633100B2

    公开(公告)日:2014-01-21

    申请号:US13163643

    申请日:2011-06-17

    IPC分类号: H01L21/768

    摘要: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming a connection post on the substrate, the connection post having a post top and a post side; mounting an integrated circuit die on the substrate, the integrated circuit die having a top die surface; molding an encapsulation on the integrated circuit die and the connection post; and forming a connector recess in the encapsulation by removing the encapsulation around the connection post exposing a portion of the post side.

    摘要翻译: 一种集成电路封装系统的制造方法,包括:提供基板; 在所述基板上形成连接柱,所述连接柱具有柱顶和柱侧; 在基板上安装集成电路管芯,集成电路管芯具有顶部管芯表面; 在集成电路管芯和连接柱上成型封装; 以及通过去除暴露一部分柱侧的连接柱周围的封装而在封装中形成连接器凹部。

    INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SUPPORT STRUCTURE AND METHOD OF MANUFACTURE THEREOF
    5.
    发明申请
    INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SUPPORT STRUCTURE AND METHOD OF MANUFACTURE THEREOF 有权
    具有支持结构的集成电路包装系统及其制造方法

    公开(公告)号:US20120319286A1

    公开(公告)日:2012-12-20

    申请号:US13163643

    申请日:2011-06-17

    IPC分类号: H01L23/48 H01L21/56

    摘要: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming a connection post on the substrate, the connection post having a post top and a post side; mounting an integrated circuit die on the substrate, the integrated circuit die having a top die surface; molding an encapsulation on the integrated circuit die and the connection post; and forming a connector recess in the encapsulation by removing the encapsulation around the connection post exposing a portion of the post side.

    摘要翻译: 一种集成电路封装系统的制造方法,包括:提供基板; 在所述基板上形成连接柱,所述连接柱具有柱顶和柱侧; 在基板上安装集成电路管芯,集成电路管芯具有顶部管芯表面; 在集成电路管芯和连接柱上成型封装; 以及通过去除暴露一部分柱侧的连接柱周围的封装而在封装中形成连接器凹部。

    Interposer substrate designs for semiconductor packages

    公开(公告)号:US09905491B1

    公开(公告)日:2018-02-27

    申请号:US14039938

    申请日:2013-09-27

    CPC分类号: H01L23/3128

    摘要: Semiconductor packages with multiple substrates can incorporate cavities in a portion of an upper substrate to minimize or reduce void formations during a molding process. The cavities can be formed substantially over the integrated circuit devices and not over the internal interconnects to further facilitate the flow of the molding compound. The combination with extension members or recesses on a top or exterior surface of the upper substrate can further cut down on bleeding or spill over of the molding compound between adjacent packages and improve device reliability and yield.