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公开(公告)号：US11688670B2
公开(公告)日：2023-06-27
申请号：US17079587
申请日：2020-10-26
IPC分类号： H01L23/48 , H01L21/283 , H01L23/495 , H01L23/00 , H01L21/78
CPC分类号： H01L23/49513 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/83 , H01L21/78 , H01L23/49579 , H01L2224/2745 , H01L2224/29109 , H01L2224/29111 , H01L2224/29139 , H01L2224/29144 , H01L2224/29147 , H01L2224/29155 , H01L2224/32245 , H01L2224/32507 , H01L2224/8381 , H01L2224/8382 , H01L2224/83203 , H01L2924/10272 , H01L2924/15747
摘要： A semiconductor package includes a power semiconductor chip comprising SiC, a leadframe part comprising Cu, wherein the power semiconductor chip is arranged on the leadframe part, and a solder joint electrically and mechanically coupling the power semiconductor chip to the leadframe part, wherein the solder joint comprises at least one intermetallic phase.
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公开(公告)号：US20230411336A1
公开(公告)日：2023-12-21
申请号：US18364483
申请日：2023-08-03
发明人： Carsten von Koblinski , Daniel Pedone , Matteo Piccin , Roland Rupp , Chiew Li Tai , Jia Yi Wong
IPC分类号： H01L23/00
CPC分类号： H01L24/37 , H01L24/29 , H01L24/73 , H01L24/83 , H01L24/84 , H01L2224/84345 , H01L2224/29021 , H01L2224/37012 , H01L2224/3702 , H01L2224/73213 , H01L2224/83851 , H01L24/94
摘要： A semiconductor wafer includes: a first main surface and a second main surface opposite the first main surface; a detachment plane parallel to the first main surface inside the semiconductor wafer, the detachment plane defined by defects; electronic semiconductor components formed at the first main surface and between the first main surface and the detachment plane; and a glass structure attached to the first main surface. The glass structure includes openings, each of which leaves a respective area of the electronic semiconductor components uncovered. A method of processing the wafer, a clip, and a semiconductor device are also described.
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3.发明申请Insulated Gate Bipolar Transistor Comprising Negative Temperature Coefficient Thermistor 有权绝缘栅双极晶体管，包括负温度系数热敏电阻公开(公告)号：US20160111415A1
公开(公告)日：2016-04-21
申请号：US14880924
申请日：2015-10-12
发明人： Thomas Basler , Erich Griebl , Joachim Mahler , Daniel Pedone , Wolfgang Scholz , Philipp Seng , Peter Tuerkes , Stephan Voss
IPC分类号： H01L27/02 , H01L29/08 , H01L29/10 , H01L29/739 , H01L21/306 , H01L49/02 , H01L29/66 , H01L29/417 , H01L27/06
CPC分类号： H01L27/0288 , H01L27/0629 , H01L29/0834 , H01L29/66348 , H01L29/7395 , H01L29/7397
摘要： An embodiment of an IGBT comprises an emitter terminal at a first surface of a semiconductor body. The IGBT further comprises a collector terminal at a second surface of the semiconductor body. A first zone of a first conductivity type is in the semiconductor body between the first and second surfaces. A collector injection structure adjoins the second surface, the collector injection structure being of a second conductivity type and comprising a first part and a second part at a first lateral distance from each other. The IGBT further comprises a negative temperature coefficient thermistor adjoining the first zone in an area between the first and second parts.
摘要翻译： IGBT的实施例包括在半导体本体的第一表面处的发射极端子。 IGBT还包括在半导体本体的第二表面处的集电极端子。 第一导电类型的第一区域位于第一和第二表面之间的半导体本体中。 集电体注入结构毗邻第二表面，集电体注入结构是第二导电类型，并且包括彼此处于第一横向距离的第一部分和第二部分。 IGBT还包括在第一和第二部分之间的区域中与第一区相邻的负温度系数热敏电阻。
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4.发明授权公开(公告)号：US11756917B2
公开(公告)日：2023-09-12
申请号：US17202990
申请日：2021-03-16
发明人： Carsten von Koblinski , Daniel Pedone , Matteo Piccin , Roland Rupp , Chiew Li Tai , Jia Yi Wong
IPC分类号： H01L23/00
CPC分类号： H01L24/37 , H01L24/29 , H01L24/73 , H01L24/83 , H01L24/84 , H01L24/94 , H01L2224/29021 , H01L2224/3702 , H01L2224/37012 , H01L2224/73213 , H01L2224/83851 , H01L2224/84345
摘要： A method for processing a semiconductor wafer is provided. A semiconductor wafer includes a first main surface and a second main surface. Defects are generated inside the semiconductor wafer to define a detachment plane parallel to the first main surface. Processing the first main surface defines a plurality of electronic semiconductor components. A glass structure is provided which includes a plurality of openings. The glass structure is attached to the processed first main surface, each of the plurality of openings leaving a respective area of the plurality of electronic semiconductor components uncovered. A polymer layer is applied to the second main surface and the semiconductor wafer is split into a semiconductor slice and a remaining semiconductor wafer by cooling the polymer layer beneath its glass transition temperature along the detachment plane. The semiconductor slice includes the plurality of electronic semiconductor components.
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5.发明申请公开(公告)号：US20210305198A1
公开(公告)日：2021-09-30
申请号：US17202990
申请日：2021-03-16
发明人： Carsten von Koblinski , Daniel Pedone , Matteo Piccin , Roland Rupp , Chiew Li Tai , Jia Yi Wong
IPC分类号： H01L23/00
摘要： A method for processing a semiconductor wafer is provided. A semiconductor wafer includes a first main surface and a second main surface. Defects are generated inside the semiconductor wafer to define a detachment plane parallel to the first main surface. Processing the first main surface defines a plurality of electronic semiconductor components. A glass structure is provided which includes a plurality of openings. The glass structure is attached to the processed first main surface, each of the plurality of openings leaving a respective area of the plurality of electronic semiconductor components uncovered. A polymer layer is applied to the second main surface and the semiconductor wafer is split into a semiconductor slice and a remaining semiconductor wafer by cooling the polymer layer beneath its glass transition temperature along the detachment plane. The semiconductor slice includes the plurality of electronic semiconductor components.
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公开(公告)号：US20160133620A1
公开(公告)日：2016-05-12
申请号：US14920374
申请日：2015-10-22
发明人： Daniel Pedone , Hans-Joachim Schulze , Rolf Gerlach , Christian Kasztelan , Anton Mauder , Hubert Rothleitner , Wolfgang Scholz , Philipp Seng , Peter Tuerkes
IPC分类号： H01L27/02 , H01L21/8234 , H01L29/866 , H01L21/8249 , H01L27/06 , H01L29/739
CPC分类号： H01L27/0259 , H01L21/8249 , H01L27/0255 , H01L27/0623 , H01L27/0629 , H01L29/7393 , H01L29/7397 , H01L29/866
摘要： A temperature protected power semiconductor device has a substrate which includes a power field effect transistor (FET) and a thermosensitive element. The power FET has a gate electrode connected to a gate, a drift region, and first and second terminals for a load current. The load current is controllable during operation by a voltage applied between the gate and the first terminal. The thermosensitive element has a first contact connected to one of the gate electrode and first terminal of the power FET, and a second contact connected to the other one of the gate electrode and first terminal. The thermosensitive element is located close to the power FET and thermally coupled thereto. The thermosensitive element is configured to cause the power FET to reduce the load current in case of an exceedance of a limit temperature of the power FET, by interconnecting the gate and first terminal.
摘要翻译： 温度保护功率半导体器件具有包括功率场效应晶体管（FET）和热敏元件的衬底。 功率FET具有连接到栅极，漂移区域的栅极电极和用于负载电流的第一和第二端子。 通过施加在栅极和第一端子之间的电压在工作期间负载电流是可控的。 热敏元件具有连接到功率FET的栅极电极和第一端子中的一个的第一触点，以及连接到栅电极和第一端子中的另一个的第二触点。 热敏元件靠近功率FET并与其热耦合。 热敏元件被配置为通过互连栅极和第一端子而使功率FET在功率FET的极限温度超过的情况下减小负载电流。
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公开(公告)号：US20240096842A1
公开(公告)日：2024-03-21
申请号：US18522991
申请日：2023-11-29
发明人： Ralf Otremba , Gregor Langer , Paul Frank , Alexander Heinrich , Alexandra Ludsteck-Pechloff , Daniel Pedone
IPC分类号： H01L23/00 , H01L23/495 , H01L23/498
CPC分类号： H01L24/32 , H01L23/49582 , H01L23/49866 , H01L24/05 , H01L24/83 , H01L2224/04026 , H01L2224/05082 , H01L2224/05155 , H01L2224/05639 , H01L2224/05644 , H01L2224/05655 , H01L2224/05669 , H01L2224/32258 , H01L2224/32503 , H01L2224/32507 , H01L2224/83203 , H01L2224/83439 , H01L2224/83444 , H01L2224/83455 , H01L2224/83464 , H01L2224/83486 , H01L2224/8382 , H01L2924/01028 , H01L2924/01047 , H01L2924/0105 , H01L2924/01327 , H01L2924/10272
摘要： A method for fabricating a SiC power semiconductor device includes: providing a SiC power semiconductor die; depositing a metallization layer over the power semiconductor die, the metallization layer including a first metal; arranging the power semiconductor die over a die carrier such that the metallization layer faces the die carrier, the die carrier being at least partially covered by a plating that includes Ni; and diffusion soldering the power semiconductor die to the die carrier such that a first intermetallic compound is formed between the power semiconductor die and the plating, the first intermetallic compound including Ni3Sn4.
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公开(公告)号：US20210225795A1
公开(公告)日：2021-07-22
申请号：US17150026
申请日：2021-01-15
发明人： Ralf Otremba , Gregor Langer , Paul Frank , Alexander Heinrich , Alexandra Ludsteck-Pechloff , Daniel Pedone
IPC分类号： H01L23/00 , H01L23/498 , H01L23/495
摘要： A SiC power semiconductor device includes: a power semiconductor die including SiC and a metallization layer, wherein the metallization layer includes a first metal; a die carrier, wherein the power semiconductor die is arranged over the die carrier such that the metallization layer faces the die carrier, the die carrier being at least partially covered by a plating that includes Ni; and a first intermetallic compound arranged between the power semiconductor die and the plating and including Ni3Sn4.
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公开(公告)号：US20230290709A1
公开(公告)日：2023-09-14
申请号：US18197800
申请日：2023-05-16
IPC分类号： H01L23/495 , H01L23/00 , H01L21/78
CPC分类号： H01L23/49513 , H01L24/29 , H01L24/83 , H01L24/32 , H01L24/27 , H01L2224/29147 , H01L2224/29155 , H01L2224/32245 , H01L2224/29111 , H01L21/78 , H01L2224/29139 , H01L2224/8381 , H01L2924/10272 , H01L2224/2745 , H01L2224/8382 , H01L2924/15747 , H01L2224/29109 , H01L23/49579 , H01L2224/32507 , H01L2224/83203 , H01L2224/29144
摘要： A semiconductor package includes a power semi conductor chip comprising SiC, a leadframe part including Cu, wherein the power semiconductor chip is arranged on the leadframe part, and a solder joint electrically and mechanically coupling the power semiconductor chip to the leadframe part, wherein the solder joint includes at least one intermetallic phase.
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公开(公告)号：US11276680B2
公开(公告)日：2022-03-15
申请号：US14920374
申请日：2015-10-22
发明人： Daniel Pedone , Hans-Joachim Schulze , Rolf Gerlach , Christian Kasztelan , Anton Mauder , Hubert Rothleitner , Wolfgang Scholz , Philipp Seng , Peter Tuerkes
IPC分类号： H01L27/02 , H01L27/06 , H01L29/739 , H01L29/866 , H01L21/8249
摘要： A temperature protected power semiconductor device has a substrate which includes a power field effect transistor (FET) and a thermosensitive element. The power FET has a gate electrode connected to a gate, a drift region, and first and second terminals for a load current. The load current is controllable during operation by a voltage applied between the gate and the first terminal. The thermosensitive element has a first contact connected to one of the gate electrode and first terminal of the power FET, and a second contact connected to the other one of the gate electrode and first terminal. The thermosensitive element is located close to the power FET and thermally coupled thereto. The thermosensitive element is configured to cause the power FET to reduce the load current in case of an exceedance of a limit temperature of the power FET, by interconnecting the gate and first terminal.
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