-
公开(公告)号：US20230411336A1
公开(公告)日：2023-12-21
申请号：US18364483
申请日：2023-08-03
发明人： Carsten von Koblinski , Daniel Pedone , Matteo Piccin , Roland Rupp , Chiew Li Tai , Jia Yi Wong
IPC分类号： H01L23/00
CPC分类号： H01L24/37 , H01L24/29 , H01L24/73 , H01L24/83 , H01L24/84 , H01L2224/84345 , H01L2224/29021 , H01L2224/37012 , H01L2224/3702 , H01L2224/73213 , H01L2224/83851 , H01L24/94
摘要： A semiconductor wafer includes: a first main surface and a second main surface opposite the first main surface; a detachment plane parallel to the first main surface inside the semiconductor wafer, the detachment plane defined by defects; electronic semiconductor components formed at the first main surface and between the first main surface and the detachment plane; and a glass structure attached to the first main surface. The glass structure includes openings, each of which leaves a respective area of the electronic semiconductor components uncovered. A method of processing the wafer, a clip, and a semiconductor device are also described.
-
公开(公告)号：US09245684B2
公开(公告)日：2016-01-26
申请号：US13972656
申请日：2013-08-21
CPC分类号： H01F41/04 , H01F27/2804 , H01F41/041 , H01F2027/2819 , H01L2924/0002 , Y10T29/4902 , H01L2924/00
摘要： A method for manufacturing a transformer device includes providing a glass substrate having a first side and a second side arranged opposite the first side, forming a first recess in the glass substrate at the first side of the glass substrate, forming a second recess in the glass substrate at the second side of the glass substrate opposite to the first recess, forming a first coil in the first recess, and forming a second coil in the second recess.
摘要翻译： 一种变压器装置的制造方法，其特征在于，提供具有与所述第一侧相对配置的第一侧和第二侧的玻璃基板，在所述玻璃基板的所述第一侧的所述玻璃基板中形成第一凹部，在所述玻璃基板的第二侧形成第二凹部 基板在与第一凹部相对的玻璃基板的第二面处，在第一凹部中形成第一线圈，并在第二凹部中形成第二线圈。
-
3.发明授权公开(公告)号：US11069639B2
公开(公告)日：2021-07-20
申请号：US16282401
申请日：2019-02-22
IPC分类号： H01L23/00 , H01L21/56 , H01L21/48 , H01L23/31 , H01L25/16 , H01L25/07 , H01L23/29 , H01L23/538 , H01L21/78 , H01L21/683 , H01L27/088
摘要： In an embodiment, a module includes a first electronic device in a first device region and a second electronic device in a second device region. The first electronic device is operably coupled to the second electronic device to form a circuit. Side faces of the first electronic device and of the second electronic device are embedded in, and in direct contact with, a first epoxy layer.
-
4.发明授权公开(公告)号：US08803312B2
公开(公告)日：2014-08-12
申请号：US13966492
申请日：2013-08-14
CPC分类号： H01L23/49811 , H01L21/56 , H01L21/561 , H01L21/568 , H01L21/78 , H01L23/3107 , H01L23/3135 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L29/7802 , H01L29/8611 , H01L2224/02122 , H01L2224/03015 , H01L2224/03019 , H01L2224/0332 , H01L2224/0345 , H01L2224/0346 , H01L2224/03462 , H01L2224/03464 , H01L2224/03848 , H01L2224/04042 , H01L2224/05124 , H01L2224/05139 , H01L2224/05166 , H01L2224/05553 , H01L2224/05554 , H01L2224/05571 , H01L2224/05647 , H01L2224/0603 , H01L2224/06181 , H01L2224/32225 , H01L2224/3223 , H01L2224/32245 , H01L2224/48227 , H01L2224/4823 , H01L2224/48247 , H01L2224/48463 , H01L2224/4903 , H01L2224/73265 , H01L2224/94 , H01L2924/00014 , H01L2924/01068 , H01L2924/01078 , H01L2924/10253 , H01L2924/10271 , H01L2924/10272 , H01L2924/10329 , H01L2924/1033 , H01L2924/10331 , H01L2924/10335 , H01L2924/10338 , H01L2924/10351 , H01L2924/10373 , H01L2924/12042 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13062 , H01L2924/15788 , H01L2924/181 , H01L2924/3511 , H01L2924/00012 , H01L2224/03 , H01L2924/00 , H01L2224/05552 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method for manufacturing semiconductor devices is disclosed. A semiconductor wafer is provided having a first surface and a second surface opposite to the first surface. A first glass substrate is provided which has at least one of cavities and openings at the bonding surface. The first glass substrate is bonded to the first surface of the semiconductor wafer such that the metal pads are arranged within respective cavities or openings of the first glass substrate. The second surface of the semiconductor wafer is machined. At least one metallization region is formed on the machined second surface of the semiconductor wafer.
摘要翻译： 公开了半导体器件的制造方法。 提供了具有与第一表面相对的第一表面和第二表面的半导体晶片。 提供了在接合表面处具有至少一个空腔和开口的第一玻璃基板。 将第一玻璃基板接合到半导体晶片的第一表面，使得金属焊盘被布置在第一玻璃基板的相应空腔或开口内。 加工半导体晶片的第二表面。 在半导体晶片的加工的第二表面上形成至少一个金属化区域。
-
公开(公告)号：US20210335739A1
公开(公告)日：2021-10-28
申请号：US17369292
申请日：2021-07-07
IPC分类号： H01L23/00 , H01L21/48 , H01L21/56 , H01L21/78 , H01L23/29 , H01L23/31 , H01L23/538 , H01L25/07 , H01L25/16 , H01L21/683 , H01L27/088
摘要： In an embodiment, a semiconductor package includes a first transistor device having first and second opposing surfaces, a first power electrode and a control electrode arranged on the first surface and a second power electrode arranged on the second surface. A first metallization structure arranged on the first surface includes a plurality of outer contact pads which includes a protective layer of solder, Ag or Sn. A second metallization structure is arranged on the second surface. A conductive connection extending from the first surface to the second surface electrically connects the second power electrode to an outer contact pad of the first metallization structure. A first epoxy layer arranged on side faces and on the first surface of the transistor device includes openings which define a lateral size of the plurality of outer contact pads and a package footprint.
-
公开(公告)号：US20190267362A1
公开(公告)日：2019-08-29
申请号：US16282420
申请日：2019-02-22
IPC分类号： H01L25/16 , H01L23/31 , H01L23/538 , H01L21/48 , H01L21/56
摘要： In an embodiment, a semiconductor package includes a first transistor device having first and second opposing surfaces, a first power electrode and a control electrode arranged on the first surface and a second power electrode arranged on the second surface. A first metallization structure arranged on the first surface includes a plurality of outer contact pads which includes a protective layer of solder, Ag or Sn. A second metallization structure is arranged on the second surface. A conductive connection extending from the first surface to the second surface electrically connects the second power electrode to an outer contact pad of the first metallization structure. A first epoxy layer arranged on side faces and on the first surface of the transistor device includes openings which define a lateral size of the plurality of outer contact pads and a package footprint.
-
公开(公告)号：US12087717B2
公开(公告)日：2024-09-10
申请号：US17369292
申请日：2021-07-07
IPC分类号： H01L21/48 , H01L21/56 , H01L21/683 , H01L21/78 , H01L23/00 , H01L23/29 , H01L23/31 , H01L23/538 , H01L25/07 , H01L25/16 , H01L27/088
CPC分类号： H01L24/08 , H01L21/4857 , H01L21/486 , H01L21/56 , H01L21/561 , H01L21/6835 , H01L21/78 , H01L23/293 , H01L23/3135 , H01L23/3178 , H01L23/3185 , H01L23/5383 , H01L23/5384 , H01L23/5389 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/24 , H01L24/25 , H01L24/73 , H01L24/82 , H01L24/96 , H01L25/072 , H01L25/16 , H01L27/088 , H01L23/3107 , H01L24/48 , H01L2221/68327 , H01L2221/6834 , H01L2224/0231 , H01L2224/0233 , H01L2224/02381 , H01L2224/04042 , H01L2224/05553 , H01L2224/05647 , H01L2224/0603 , H01L2224/06182 , H01L2224/08137 , H01L2224/24105 , H01L2224/24137 , H01L2224/245 , H01L2224/2518 , H01L2224/48247 , H01L2224/49175 , H01L2224/73227 , H01L2924/13055 , H01L2924/13091 , H01L2224/245 , H01L2924/01029 , H01L2924/13091 , H01L2924/00 , H01L2924/13055 , H01L2924/00
摘要： In an embodiment, a semiconductor package includes a first transistor device having first and second opposing surfaces, a first power electrode and a control electrode arranged on the first surface and a second power electrode arranged on the second surface. A first metallization structure arranged on the first surface includes a plurality of outer contact pads which includes a protective layer of solder, Ag or Sn. A second metallization structure is arranged on the second surface. A conductive connection extending from the first surface to the second surface electrically connects the second power electrode to an outer contact pad of the first metallization structure. A first epoxy layer arranged on side faces and on the first surface of the transistor device includes openings which define a lateral size of the plurality of outer contact pads and a package footprint.
-
公开(公告)号：US11081457B2
公开(公告)日：2021-08-03
申请号：US16282420
申请日：2019-02-22
IPC分类号： H01L25/16 , H01L23/31 , H01L23/538 , H01L21/48 , H01L21/56 , H01L23/00 , H01L21/78 , H01L23/29 , H01L25/07 , H01L21/683 , H01L27/088
摘要： In an embodiment, a semiconductor package includes a first transistor device having first and second opposing surfaces, a first power electrode and a control electrode arranged on the first surface and a second power electrode arranged on the second surface. A first metallization structure arranged on the first surface includes a plurality of outer contact pads which includes a protective layer of solder, Ag or Sn. A second metallization structure is arranged on the second surface. A conductive connection extending from the first surface to the second surface electrically connects the second power electrode to an outer contact pad of the first metallization structure. A first epoxy layer arranged on side faces and on the first surface of the transistor device includes openings which define a lateral size of the plurality of outer contact pads and a package footprint.
-
9.发明申请公开(公告)号：US20190267343A1
公开(公告)日：2019-08-29
申请号：US16282401
申请日：2019-02-22
IPC分类号： H01L23/00 , H01L21/56 , H01L21/48 , H01L23/31 , H01L25/16 , H01L25/07 , H01L23/29 , H01L23/538 , H01L21/78
摘要： In an embodiment, a module includes a first electronic device in a first device region and a second electronic device in a second device region. The first electronic device is operably coupled to the second electronic device to form a circuit. Side faces of the first electronic device and of the second electronic device are embedded in, and in direct contact with, a first epoxy layer.
-
10.发明授权公开(公告)号：US08865522B2
公开(公告)日：2014-10-21
申请号：US13865579
申请日：2013-04-18
IPC分类号： H01L21/00 , H01L21/30 , H01L23/12 , H01L23/06 , H01L23/495 , H01L21/56 , H01L23/00 , H01L23/31 , H01L21/78 , H01L29/78 , H01L29/861
CPC分类号： H01L24/83 , H01L21/56 , H01L21/561 , H01L21/568 , H01L21/78 , H01L23/3107 , H01L23/3135 , H01L23/49534 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L29/7802 , H01L29/8611 , H01L2224/02122 , H01L2224/03015 , H01L2224/03019 , H01L2224/0332 , H01L2224/0345 , H01L2224/0346 , H01L2224/03462 , H01L2224/03464 , H01L2224/03848 , H01L2224/04042 , H01L2224/05124 , H01L2224/05139 , H01L2224/05166 , H01L2224/05553 , H01L2224/05571 , H01L2224/05647 , H01L2224/0603 , H01L2224/06181 , H01L2224/27013 , H01L2224/29101 , H01L2224/2929 , H01L2224/32225 , H01L2224/3223 , H01L2224/32245 , H01L2224/32503 , H01L2224/32507 , H01L2224/48091 , H01L2224/48227 , H01L2224/4823 , H01L2224/48247 , H01L2224/48463 , H01L2224/4903 , H01L2224/73265 , H01L2224/83192 , H01L2224/8381 , H01L2224/83815 , H01L2224/83862 , H01L2224/8389 , H01L2224/94 , H01L2924/00014 , H01L2924/01068 , H01L2924/01078 , H01L2924/01322 , H01L2924/01327 , H01L2924/0781 , H01L2924/10253 , H01L2924/10271 , H01L2924/10272 , H01L2924/10329 , H01L2924/1033 , H01L2924/10331 , H01L2924/10335 , H01L2924/10338 , H01L2924/10351 , H01L2924/10373 , H01L2924/12042 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13062 , H01L2924/15788 , H01L2924/181 , H01L2924/3511 , H01L2924/00012 , H01L2224/03 , H01L2924/00 , H01L2224/45099 , H01L2924/014 , H01L2224/05552
摘要： A method for connecting a semiconductor chip to a metal layer of a carrier substrate is disclosed. A semiconductor chip is provided which has a first side, a second side opposite the first side, a glass substrate bonded to the second side of the semiconductor chip and including at least one opening leaving an area of the second side of the semiconductor chip uncovered by the glass substrate, and a metallization region arranged in the opening of the glass substrate and electrically contacting the second side of the semiconductor chip. The semiconductor chip with the bonded glass substrate is brought onto a metal layer of a carrier substrate. A firm mechanical and electrical connection is formed between the metal layer of the carrier substrate and the metallization region.
摘要翻译： 公开了一种用于将半导体芯片连接到载体衬底的金属层的方法。 提供一种半导体芯片，其具有第一侧，与第一侧相对的第二侧，接合到半导体芯片的第二侧的玻璃基板，并且包括至少一个开口，留下半导体芯片的第二面的区域， 玻璃基板和布置在玻璃基板的开口中的金属化区域，并与半导体芯片的第二面电接触。 具有粘合玻璃基板的半导体芯片被带到载体基板的金属层上。 在载体基板的金属层和金属化区域之间形成牢固的机械和电连接。
-
-
-
-
-
-
-
-
-
搜索结果
15 条记录 (耗时 0.023 秒)
