公开(公告)号：US20240213074A1

公开(公告)日：2024-06-27

申请号：US18089468

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Mark SALTAS ,  Edvin CETEGEN ,  Tony DAMBRAUSKAS ,  Albert KAMGA ,  Mine KAYA ,  James MELLODY ,  Rajesh Kumar NEERUKATTI

IPC: H01L21/683 ,  B25J15/06

CPC classification number: H01L21/6838 ,  B25J15/0616 ,  H01L2224/81203

Abstract: This disclosure describes nozzle designs for holding disaggregated die flat in a bonding process. The nozzle designs may have trenches extending radially outward from the center of the nozzle to the corners, such as in a snowflake pattern. The trenches may be positioned to be axially unaligned with any mold dishes of the disaggregated die when lifting the disaggregated die. The trenches may have a depth of at least 200 micrometers to allow for sufficient air flow to prevent warpage of the disaggregated die.

公开(公告)号：US20250112136A1

公开(公告)日：2025-04-03

申请号：US18374937

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Bohan SHAN ,  Jesse JONES ,  Zhixin XIE ,  Bai NIE ,  Shaojiang CHEN ,  Joshua STACEY ,  Mitchell PAGE ,  Brandon C. MARIN ,  Jeremy D. ECTON ,  Nicholas S. HAEHN ,  Astitva TRIPATHI ,  Yuqin LI ,  Edvin CETEGEN ,  Jason M. GAMBA ,  Jacob VEHONSKY ,  Jianyong MO ,  Makoyi WATSON ,  Shripad GOKHALE ,  Mine KAYA ,  Kartik SRINIVASAN ,  Haobo CHEN ,  Ziyin LIN ,  Kyle ARRINGTON ,  Jose WAIMIN ,  Ryan CARRAZZONE ,  Hongxia FENG ,  Srinivas Venkata Ramanuja PIETAMBARAM ,  Gang DUAN ,  Dingying David XU ,  Hiroki TANAKA ,  Ashay DANI ,  Praveen SREERAMAGIRI ,  Yi LI ,  Ibrahim EL KHATIB ,  Aaron GARELICK ,  Robin MCREE ,  Hassan AJAMI ,  Yekan WANG ,  Andrew JIMENEZ ,  Jung Kyu HAN ,  Hanyu SONG ,  Yonggang Yong LI ,  Mahdi MOHAMMADIGHALENI ,  Whitney BRYKS ,  Shuqi LAI ,  Jieying KONG ,  Thomas HEATON ,  Dilan SENEVIRATNE ,  Yiqun BAI ,  Bin MU ,  Mohit GUPTA ,  Xiaoying GUO

IPC: H01L23/498 ,  H01L23/15

Abstract: Embodiments disclosed herein include apparatuses with glass core package substrates. In an embodiment, an apparatus comprises a substrate with a first surface and a second surface opposite from the first surface. A sidewall is between the first surface and the second surface, and the substrate comprises a glass layer. In an embodiment, a via is provided through the substrate between the first surface and the second surface, and the via is electrically conductive. In an embodiment, a layer in contact with the sidewall of the substrate surrounds a perimeter of the substrate.

公开(公告)号：US20240186251A1

公开(公告)日：2024-06-06

申请号：US18075360

申请日：2022-12-05

Applicant: Intel Corporation

Inventor： Minglu LIU ,  YANG WU ,  Yuting WANG ,  Lawrence ROSS ,  Mine KAYA ,  Gang DUAN ,  Edvin CETEGEN ,  Alexander AGUINAGA

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/13 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L23/13 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0655 ,  H01L24/81 ,  H01L2224/16227 ,  H01L2224/81203 ,  H01L2924/351

Abstract: Embodiments disclosed herein include package architectures. In an embodiment, the package architecture comprises a package substrate, a first bridge in the package substrate, where the first bridge includes conductive routing, and a second bridge in the package substrate. In an embodiment, the package architecture further comprises a third bridge in the package substrate, where the second bridge and the third bridge are positioned symmetrically about the first bridge.

公开(公告)号：US20250112164A1

公开(公告)日：2025-04-03

申请号：US18374932

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Bohan SHAN ,  Onur OZKAN ,  Ryan CARRAZZONE ,  Rui ZHANG ,  Haobo CHEN ,  Ziyin LIN ,  Yiqun BAI ,  Kyle ARRINGTON ,  Jose WAIMIN ,  Hongxia FENG ,  Srinivas Venkata Ramanuja PIETAMBARAM ,  Gang DUAN ,  Dingying David XU ,  Bin MU ,  Mohit GUPTA ,  Jeremy D. ECTON ,  Brandon C. MARIN ,  Xiaoying GUO ,  Steve S. CHO ,  Ali LEHAF ,  Venkata Rajesh SARANAM ,  Shripad GOKHALE ,  Kartik SRINIVASAN ,  Edvin CETEGEN ,  Mine KAYA ,  Nicholas S. HAEHN ,  Deniz TURAN

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065

Abstract: A device comprises a substrate comprising a plurality of build-up layers and a cavity. A bridge die is located within the cavity and a plurality of cavity side bumps are on one side of the bridge die. A plurality of interconnect pads with variable heights are on one of the build-up layers of the substrate coupled to the plurality of the cavity side bumps to bond the bridge die to the substrate.

公开(公告)号：US20240186280A1

公开(公告)日：2024-06-06

申请号：US18060596

申请日：2022-12-01

Applicant: Intel Corporation

Inventor： Minglu LIU ,  Andrey GUNAWAN ,  Gang DUAN ,  Edvin CETEGEN ,  Yuting WANG ,  Mine KAYA ,  Kartik SRINIVASAN ,  Mihir OKA ,  Anurag TRIPATHI

IPC: H01L23/00

CPC classification number: H01L24/75 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/7598 ,  H01L2224/75985 ,  H01L2224/81093 ,  H01L2224/81097 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/95093 ,  H01L2224/97 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2924/3841

Abstract: The present disclosure is directed to an apparatus having a bond head configured to heat and compress a semiconductor package assembly, and a bonding stage configured to hold the semiconductor package assembly, wherein the bonding stage comprises a ceramic material including silicon and either magnesium or indium.