公开(公告)号：US10281521B2

公开(公告)日：2019-05-07

申请号：US15367415

申请日：2016-12-02

Applicant: Intel Corporation

Inventor： David Won-jun Song ,  James R. Hastings ,  Akhilesh P. Rallabandi ,  Morten S. Jensen ,  Christopher Wade Ackerman ,  Christopher R. Schroeder ,  Nader N. Abazarnia ,  John C. Johnson

IPC: G01R31/10 ,  G01R31/28 ,  H05B6/10

Abstract: Techniques for thermal management of a device under test are discussed. In an example, an apparatus may include a pedestal having a device-specific surface configured to exchange heat with the integrated circuit while the device-specific surface is in contact with a surface of the integrated circuit or separated from the surface of the integrated circuit by a layer of thermally conductive material, and a heat generating element configured to heat the device-specific surface. In certain examples, the pedestal may include a plurality of channels configured to couple to a manifold and to route thermal material from the manifold through an interior of the pedestal for maintaining temperature control of the surface of an integrated circuit under test.

公开(公告)号：US09496161B2

公开(公告)日：2016-11-15

申请号：US15050387

申请日：2016-02-22

Applicant: INTEL CORPORATION

Inventor： John C. Johnson ,  Eric J. Moret ,  Lawrence M. Palanuk ,  Gregory A. Stone

IPC: H01L21/67 ,  H01L21/78 ,  H01L21/673 ,  H01L21/677 ,  H01L21/683 ,  H01L21/687 ,  H05K13/00 ,  H01L21/68

CPC classification number: H01L21/67333 ,  H01L21/67265 ,  H01L21/67309 ,  H01L21/67356 ,  H01L21/67363 ,  H01L21/67383 ,  H01L21/67769 ,  H01L21/67772 ,  H01L21/67778 ,  H01L21/68 ,  H01L21/6833 ,  H01L21/68764 ,  H01L21/68771 ,  H01L21/78 ,  H05K13/0084

Abstract: A method includes identifying a wafer position for a plurality of die on a wafer, storing the wafer position for each of the plurality of die in a database, dicing the wafer into a plurality of singulated die, positioning each of the singulated die in a die position location on a tray, and storing the die position on the tray for each of the singulated die in the database. The database includes information including the wafer position associated with each die position. The tray is transported to a processing tool, and at least one of the plurality of singulated die is removed from the die position on the tray and processed in the processing tool. The processed singulated die is replaced in the same defined location on the tray that the singulated die was positioned in prior to the processing. Other embodiments are described and claimed.

Abstract translation: 一种方法包括识别晶片上的多个管芯的晶片位置，将多个管芯中的每个管芯的晶片位置存储在数据库中，将晶片切割成多个单个管芯，将每个单模管芯定位在管芯中 在托盘上的位置位置，并将模具位置存储在数据库中的每个单个模具的托盘上。 数据库包括包括与每个模具位置相关联的晶片位置的信息。 托盘被运送到处理工具，并且多个分割模具中的至少一个从托盘上的模具位置移除并在处理工具中进行处理。 在处理之前，单独模具位于托盘上的相同的限定位置处理被处理的单个模具。 描述和要求保护其他实施例。

公开(公告)号：US10566263B2

公开(公告)日：2020-02-18

申请号：US15718337

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Joe Walczyk ,  John C. Johnson

IPC: H01L23/427 ,  F28F1/40 ,  G01R31/26

Abstract: A heat spreader apparatus, testing system, method may be used to test an electronic device. The heat spreader may include a hollow housing. The hollow housing may define an interior chamber. The hollow housing may include a contact surface. The heat spreader may include a working fluid. The working fluid may be included in the interior chamber. The hollow housing may be configured to be physically compliant. The hollow housing may be physically compliant such that the hollow housing conforms to the shape of a testing surface in response to an applied pressure. The testing surface may be a top surface of a semiconductor. The testing surface may be curved or otherwise lack uniformity. The hollow housing may conform to the curvature or lack of uniformity of the testing surface such that minimal gaps exist between the hollow housing and the surface.

公开(公告)号：US20180156863A1

公开(公告)日：2018-06-07

申请号：US15367415

申请日：2016-12-02

Applicant: Intel Corporation

Inventor： David Won-jun Song ,  James R. Hastings ,  Akhilesh P. Rallabandi ,  Morten S. Jensen ,  Christopher Wade Ackerman ,  Christopher R. Schroeder ,  Nader N. Abazarnia ,  John C. Johnson

IPC: G01R31/28 ,  H05B6/10

CPC classification number: G01R31/2875 ,  H05B6/06 ,  H05B6/10 ,  H05B6/105

Abstract: Techniques for thermal management of a device under test are discussed. In an example, an apparatus may include a pedestal having a device-specific surface configured to exchange heat with the integrated circuit while the device-specific surface is in contact with a surface of the integrated circuit or separated from the surface of the integrated circuit by a layer of thermally conductive material, and a heat generating element configured to heat the device-specific surface. In certain examples, the pedestal may include a plurality of channels configured to couple to a manifold and to route thermal material from the manifold through an interior of the pedestal for maintaining temperature control of the surface of an integrated circuit under test.

公开(公告)号：US20190096785A1

公开(公告)日：2019-03-28

申请号：US15718337

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Joe Walczyk ,  John C. Johnson

IPC: H01L23/427 ,  F28F1/40

Abstract: A heat spreader apparatus, testing system, method may be used to test an electronic device. The heat spreader may include a hollow housing. The hollow housing may define an interior chamber. The hollow housing may include a contact surface. The heat spreader may include a working fluid. The working fluid may be included in the interior chamber. The hollow housing may be configured to be physically compliant. The hollow housing may be physically compliant such that the hollow housing conforms to the shape of a testing surface in response to an applied pressure. The testing surface may be a top surface of a semiconductor. The testing surface may be curved or otherwise lack uniformity. The hollow housing may conform to the curvature or lack of uniformity of the testing surface such that minimal gaps exist between the hollow housing and the surface.

公开(公告)号：US09929031B2

公开(公告)日：2018-03-27

申请号：US15295943

申请日：2016-10-17

Applicant: INTEL CORPORATION

Inventor： John C. Johnson ,  Eric J. Moret ,  Lawrence M. Palanuk ,  Gregory A. Stone

IPC: H01L21/673 ,  H01L21/78 ,  H01L21/677 ,  H01L21/683 ,  H01L21/687 ,  H05K13/00 ,  H01L21/68 ,  H01L21/67

CPC classification number: H01L21/67333 ,  H01L21/67265 ,  H01L21/67309 ,  H01L21/67356 ,  H01L21/67363 ,  H01L21/67383 ,  H01L21/67769 ,  H01L21/67772 ,  H01L21/67778 ,  H01L21/68 ,  H01L21/6833 ,  H01L21/68764 ,  H01L21/68771 ,  H01L21/78 ,  H05K13/0084

Abstract: A method includes identifying a wafer position for a plurality of die on a wafer, storing the wafer position for each of the plurality of die in a database, dicing the wafer into a plurality of singulated die, positioning each of the singulated die in a die position location on a tray, and storing the die position on the tray for each of the singulated die in the database. The database includes information including the wafer position associated with each die position. The tray is transported to a processing tool, and at least one of the plurality of singulated die is removed from the die position on the tray and processed in the processing tool. The processed singulated die is replaced in the same defined location on the tray that the singulated die was positioned in prior to the processing. Other embodiments are described and claimed.

公开(公告)号：US20160291083A1

公开(公告)日：2016-10-06

申请号：US15185468

申请日：2016-06-17

Applicant: INTEL CORPORATION

Inventor： John C. Johnson ,  James G. MAVEETY ,  Abram M. Detofsky ,  James E. Neeb

IPC: G01R31/28

CPC classification number: G01R31/2874 ,  G01R1/0458 ,  G01R1/06722 ,  G01R1/06783 ,  G01R1/44 ,  G01R31/2642 ,  G01R31/2875 ,  G01R31/2891 ,  H05K7/20

Abstract: A thermal controller includes a thermal control interface to receive test data from an automated test equipment (ATE) system and dynamically adjust a target setpoint temperature based on the data and a dynamic thermal controller to receive the target setpoint temperature from the thermal control interface and control a thermal actuator based on the target setpoint temperature.

Abstract translation: 热控制器包括用于从自动测试设备（ATE）系统接收测试数据的热控制接口，并且基于该数据动态地调整目标设定点温度和动态热控制器以从热控制接口和控制接收目标设定点温度 基于目标设定点温度的热致动器。

公开(公告)号：US09305816B2

公开(公告)日：2016-04-05

申请号：US14142761

申请日：2013-12-28

Applicant: INTEL CORPORATION

Inventor： John C. Johnson ,  Peter A. Davison ,  Eric J. Moret ,  Lawrence M. Palanuk ,  Gregory A. Stone

IPC: H01L21/67 ,  H01L21/78 ,  H01L21/677 ,  H01L21/683 ,  H01L21/687 ,  H05K13/00 ,  H01L21/673 ,  H01L21/68

CPC classification number: H01L21/67333 ,  H01L21/67265 ,  H01L21/67309 ,  H01L21/67356 ,  H01L21/67363 ,  H01L21/67383 ,  H01L21/67769 ,  H01L21/67772 ,  H01L21/67778 ,  H01L21/68 ,  H01L21/6833 ,  H01L21/68764 ,  H01L21/68771 ,  H01L21/78 ,  H05K13/0084

Abstract: A method includes identifying a wafer position for a plurality of die on a wafer, storing the wafer position for each of the plurality of die in a database, dicing the wafer into a plurality of singulated die, positioning each of the singulated die in a die position location on a tray, and storing the die position on the tray for each of the singulated die in the database. The database includes information including the wafer position associated with each die position. The tray is transported to a processing tool, and at least one of the plurality of singulated die is removed from the die position on the tray and processed in the processing tool. The processed singulated die is replaced in the same defined location on the tray that the singulated die was positioned in prior to the processing. Other embodiments are described and claimed.

公开(公告)号：US20160027429A1

公开(公告)日：2016-01-28

申请号：US14877602

申请日：2015-10-07

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Kelin J. Kuhn ,  Debendra Mallik ,  John C. Johnson

IPC: G10K11/34

CPC classification number: G10K11/346 ,  A41D2400/00 ,  H04R1/403 ,  H04R1/406 ,  H04R2201/023 ,  H04R2201/401 ,  H04R2499/11 ,  H04R2499/15

Abstract: A system includes a processor and a phased array, coupled to the processor, having an arrayed waveguide for acoustic waves to enable directional sound communication.

Abstract translation: 系统包括耦合到处理器的处理器和相控阵列，其具有用于声波的阵列波导以实现定向声音通信。

公开(公告)号：US10074357B2

公开(公告)日：2018-09-11

申请号：US14877602

申请日：2015-10-07

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Kelin J. Kuhn ,  Debendra Mallik ,  John C. Johnson

IPC: G01K11/32 ,  G10K11/34

CPC classification number: G10K11/346 ,  A41D2400/00 ,  H04R1/403 ,  H04R1/406 ,  H04R2201/023 ,  H04R2201/401 ,  H04R2499/11 ,  H04R2499/15

Abstract: A system includes a processor and a phased array, coupled to the processor, having an arrayed waveguide for acoustic waves to enable directional sound communication.