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    CAPACITANCE MONITORING USING X-RAY DIFFRACTION
    3.
    发明申请
    CAPACITANCE MONITORING USING X-RAY DIFFRACTION 有权
    使用X射线衍射进行电容监测

    公开(公告)号：US20160178679A1

    公开(公告)日：2016-06-23

    申请号：US14575134

    申请日：2014-12-18

    申请人： International Business Machines Corporation

    发明人： Donghun Kang ,  Kriteshwar K. Kohli ,  Oh-jung Kwon ,  Anita Madan ,  Conal E. Murray

    IPC分类号： G01R27/26 ,  G01R31/265 ,  H01L21/66 ,  G01N23/20

    CPC分类号： H01L22/14 ,  G01N23/20 ,  G01N23/207 ,  G01N2223/0566 ,  G01N2223/607 ,  G01N2223/611 ,  G01R31/2656 ,  H01L22/12

    摘要： A method includes measuring a difference between a primary X-ray diffraction peak and a secondary X-ray diffraction peak, the primary X-ray diffraction peak corresponds to an unstrained portion of a semiconductor substrate and the secondary X-ray diffraction peak corresponds to a strained portion of the semiconductor substrate, the difference between the primary X-ray diffraction peak and the secondary X-ray diffraction peak includes a delta shift peak that corresponds to changes in a crystal lattice caused by a stress applied to the strained portion of the semiconductor substrate, the delta shift peak includes variations in a deep trench capacitance.

    摘要翻译： 一种方法包括测量主X射线衍射峰和次X射线衍射峰之间的差异，主X射线衍射峰对应于半导体衬底的未应变部分，并且次X射线衍射峰对应于 半导体衬底的应变部分，初级X射线衍射峰和次级X射线衍射峰之间的差包括对应于施加到半导体的应变部分的应力引起的晶格变化的δ偏移峰 衬底，δ偏移峰包括深沟槽电容的变化。

    WAFER STRESS CONTROL WITH BACKSIDE PATTERNING
    10.
    发明申请
    WAFER STRESS CONTROL WITH BACKSIDE PATTERNING 有权
    具有背面图案的波浪压力控制

    公开(公告)号：US20150364362A1

    公开(公告)日：2015-12-17

    申请号：US14306598

    申请日：2014-06-17

    申请人： International Business Machines Corporation

    发明人： Edward Engbrecht ,  Donghun Kang ,  Rishikesh Krishnan ,  Oh-jung Kwon ,  Karen A. Nummy

    IPC分类号： H01L21/762 ,  H01L21/66 ,  H01L29/06 ,  H01L21/308 ,  H01L21/321

    CPC分类号： H01L21/76227 ,  H01L21/302 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3212 ,  H01L22/12 ,  H01L29/0603 ,  H01L29/945

    摘要： Embodiments of the present invention provide structures and methods for controlling stress in semiconductor wafers during fabrication. Features such as deep trenches (DTs) used in circuit elements such as trench capacitors impart stress on a wafer that is proportional to the surface area of the DTs. In embodiments, a corresponding pattern of dummy (non-functional) DTs is formed on the back side of the wafer to counteract the electrically functional DTs formed on the front side of a wafer. In some embodiments, the corresponding pattern on the back side is a mirror pattern that matches the functional (front side) pattern in size, placement, and number. By creating the minor pattern on both sides of the wafer, the stresses on the front and back of the wafer are in balance. This helps reduce topography issues such as warping that can cause problems during wafer fabrication.

    摘要翻译： 本发明的实施例提供了在制造期间控制半导体晶片中的应力的结构和方法。 诸如沟槽电容器的电路元件中使用的诸如深沟槽（DT）的特征赋予与DT的表面积成比例的晶片上的应力。 在实施例中，虚拟（非功能）DT的相应图案形成在晶片的背面，以抵消形成在晶片正面上的电功能DT。 在一些实施例中，背面上的对应图案是与尺寸，布局和数量上的功能（前侧）图案相匹配的镜面图案。 通过在晶片的两侧形成次要图案，晶片正面和背面的应力平衡。 这有助于减少在晶圆制造过程中可能导致问题的翘曲等形貌问题。