公开(公告)号：US07468295B2

公开(公告)日：2008-12-23

申请号：US11607417

申请日：2006-12-01

申请人： Jae Yoeb Shim ,  Hyung Sup Yoon ,  Dong Min Kang ,  Ju Yeon Hong ,  Kyung Ho Lee

发明人： Jae Yoeb Shim ,  Hyung Sup Yoon ,  Dong Min Kang ,  Ju Yeon Hong ,  Kyung Ho Lee

IPC分类号： H01L21/338

CPC分类号： H01L21/0331 ,  H01L21/28587

摘要： A method of fabricating a T-gate is provided. The method includes the steps of: forming a photoresist layer on a substrate; patterning the photoresist layer formed on the substrate and forming a first opening; forming a first insulating layer on the photoresist layer and the substrate; removing the first insulating layer and forming a second opening to expose the substrate; forming a second insulating layer on the first insulating layer; removing the second insulating layer and forming a third opening to expose the substrate; forming a metal layer on the second insulating layer on which the photoresist layer and the third opening are formed; and removing the metal layer formed on the photoresist layer. Accordingly, a uniform and elaborate opening defining the length of a gate may be formed by deposition of the insulating layer and a blanket dry etching process, and thus a more elaborate micro T-gate electrode may be fabricated.

摘要翻译： 提供一种制造T型栅极的方法。 该方法包括以下步骤：在衬底上形成光致抗蚀剂层; 图案化形成在基板上的光致抗蚀剂层并形成第一开口; 在所述光致抗蚀剂层和所述基板上形成第一绝缘层; 去除所述第一绝缘层并形成第二开口以暴露所述衬底; 在所述第一绝缘层上形成第二绝缘层; 去除所述第二绝缘层并形成第三开口以暴露所述衬底; 在其上形成有光致抗蚀剂层和第三开口的第二绝缘层上形成金属层; 并除去形成在光致抗蚀剂层上的金属层。 因此，可以通过沉积绝缘层和橡皮干蚀刻工艺来形成限定栅极长度的均匀且精细的开口，因此可以制造更精细的微型T型栅电极。

公开(公告)号：US20070128752A1

公开(公告)日：2007-06-07

申请号：US11607417

申请日：2006-12-01

申请人： Jae Yoeb Shim ,  Hyung Sup Yoon ,  Dong Min Kang ,  Ju Yeon Hong ,  Kyung Ho Lee

发明人： Jae Yoeb Shim ,  Hyung Sup Yoon ,  Dong Min Kang ,  Ju Yeon Hong ,  Kyung Ho Lee

IPC分类号： H01L21/00

CPC分类号： H01L21/0331 ,  H01L21/28587

摘要： A method of fabricating a T-gate is provided. The method includes the steps of: forming a photoresist layer on a substrate; patterning the photoresist layer formed on the substrate and forming a first opening; forming a first insulating layer on the photoresist layer and the substrate; removing the first insulating layer and forming a second opening to expose the substrate; forming a second insulating layer on the first insulating layer; removing the second insulating layer and forming a third opening to expose the substrate; forming a metal layer on the second insulating layer on which the photoresist layer and the third opening are formed; and removing the metal layer formed on the photoresist layer. Accordingly, a uniform and elaborate opening defining the length of a gate may be formed by deposition of the insulating layer and a blanket dry etching process, and thus a more elaborate micro T-gate electrode may be fabricated.

摘要翻译： 提供一种制造T型栅极的方法。 该方法包括以下步骤：在衬底上形成光致抗蚀剂层; 图案化形成在基板上的光致抗蚀剂层并形成第一开口; 在所述光致抗蚀剂层和所述基板上形成第一绝缘层; 去除所述第一绝缘层并形成第二开口以暴露所述衬底; 在所述第一绝缘层上形成第二绝缘层; 去除所述第二绝缘层并形成第三开口以暴露所述衬底; 在其上形成有光致抗蚀剂层和第三开口的第二绝缘层上形成金属层; 并除去形成在光致抗蚀剂层上的金属层。 因此，可以通过沉积绝缘层和橡皮干蚀刻工艺来形成限定栅极长度的均匀且精细的开口，因此可以制造更精细的微型T型栅电极。

公开(公告)号：US07915106B2

公开(公告)日：2011-03-29

申请号：US12270016

申请日：2008-11-13

申请人： Jae Yeob Shim ,  Hyung Sup Yoon ,  Dong Min Kang ,  Ju Yeon Hong ,  Kyung Ho Lee

发明人： Jae Yeob Shim ,  Hyung Sup Yoon ,  Dong Min Kang ,  Ju Yeon Hong ,  Kyung Ho Lee

IPC分类号： H01L21/338 ,  H01L21/44 ,  H01L21/28

CPC分类号： H01L21/0331 ,  H01L21/28587

摘要： A method of fabricating a T-gate is provided. The method includes the steps of: forming a photoresist layer on a substrate; patterning the photoresist layer formed on the substrate and forming a first opening; forming a first insulating layer on the photoresist layer and the substrate; removing the first insulating layer and forming a second opening to expose the substrate; forming a second insulating layer on the first insulating layer; removing the second insulating layer and forming a third opening to expose the substrate; forming a metal layer on the second insulating layer on which the photoresist layer and the third opening are formed; and removing the metal layer formed on the photoresist layer. Accordingly, a uniform and elaborate opening defining the length of a gate may be formed by deposition of the insulating layer and a blanket dry etching process, and thus a more elaborate micro T-gate electrode may be fabricated.

摘要翻译： 提供一种制造T型栅极的方法。 该方法包括以下步骤：在衬底上形成光致抗蚀剂层; 图案化形成在基板上的光致抗蚀剂层并形成第一开口; 在所述光致抗蚀剂层和所述基板上形成第一绝缘层; 去除所述第一绝缘层并形成第二开口以暴露所述衬底; 在所述第一绝缘层上形成第二绝缘层; 去除所述第二绝缘层并形成第三开口以暴露所述衬底; 在其上形成有光致抗蚀剂层和第三开口的第二绝缘层上形成金属层; 并除去形成在光致抗蚀剂层上的金属层。 因此，可以通过沉积绝缘层和橡皮干蚀刻工艺来形成限定栅极长度的均匀且精细的开口，因此可以制造更精细的微型T型栅电极。

公开(公告)号：US08722474B2

公开(公告)日：2014-05-13

申请号：US13592589

申请日：2012-08-23

申请人： Hyung Sup Yoon ,  Byoung-Gue Min ,  Jong Min Lee ,  Seong-Il Kim ,  Dong Min Kang ,  Ho Kyun Ahn ,  Jong-Won Lim ,  Jae Kyoung Mun ,  Eun Soo Nam

发明人： Hyung Sup Yoon ,  Byoung-Gue Min ,  Jong Min Lee ,  Seong-Il Kim ,  Dong Min Kang ,  Ho Kyun Ahn ,  Jong-Won Lim ,  Jae Kyoung Mun ,  Eun Soo Nam

IPC分类号： H01L21/338

CPC分类号： H01L29/0649 ,  H01L21/28593 ,  H01L29/402 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7786

摘要： Disclosed are a semiconductor device including a stepped gate electrode and a method of fabricating the semiconductor device. The semiconductor device according to an exemplary embodiment of the present disclosure includes: a semiconductor substrate having a structure including a plurality of epitaxial layers and including an under-cut region formed in a part of a Schottky layer in an upper most part thereof; a cap layer, a first nitride layer and a second nitride layer sequentially formed on the semiconductor substrate to form a stepped gate insulating layer pattern; and a stepped gate electrode formed by depositing a heat-resistant metal through the gate insulating layer pattern, wherein the under-cut region includes an air-cavity formed between the gate electrode and the Schottky layer.

摘要翻译： 本发明公开了一种半导体器件，包括阶梯栅电极和制造该半导体器件的方法。 根据本公开的示例性实施例的半导体器件包括：半导体衬底，其具有包括多个外延层的结构，并且包括形成在其最上部的肖特基层的一部分中的下切割区域; 顺序地形成在半导体衬底上的盖层，第一氮化物层和第二氮化物层，以形成台阶栅极绝缘层图案; 以及通过栅极绝缘层图案沉积耐热金属而形成的阶梯形栅电极，其中下切区域包括形成在栅电极和肖特基层之间的空腔。

公开(公告)号：US06940354B2

公开(公告)日：2005-09-06

申请号：US10735037

申请日：2003-12-11

申请人： Dong Min Kang ,  Hyung Sup Yoon ,  Hea Cheon Kim ,  Kyoung Ik Cho

发明人： Dong Min Kang ,  Hyung Sup Yoon ,  Hea Cheon Kim ,  Kyoung Ik Cho

IPC分类号： H03F3/189 ,  H03F3/60 ,  H03F3/68 ,  H03F3/191

CPC分类号： H03F3/605

摘要： A microwave power amplifier comprising a drive amplifying stage includes power elements, gate and drain bias circuits of the power elements, a RC parallel circuit connected between input port and gates of said power elements, a shunt resistor connected between ground terminal and said gates of power elements, and a negative feedback circuit connected in series with resistors and capacitors and in parallel with the power elements. An interstage matching circuit is connected in series with the drive amplifying stage; and a power amplifying stage including power elements connected in parallel with a power divider and a power coupler, gate and drain bias circuits of said power elements, a RC parallel circuit connected between the gates of power elements and the interstage matching circuit, and a shunt resistor connected between a ground and the gates of power elements.

摘要翻译： 包括驱动放大级的微波功率放大器包括功率元件，功率元件的栅极和漏极偏置电路，连接在所述功率元件的输入端口和栅极之间的RC并联电路，连接在接地端子和所述功率门之间的分流电阻器 元件和与电阻器和电容器串联连接并与功率元件并联的负反馈电路。 级间匹配电路与驱动放大级串联; 以及功率放大级，包括与功率分配器和功率耦合器并联连接的功率元件，所述功率元件的栅极和漏极偏置电路，连接在功率元件的栅极和级间匹配电路之间的RC并联电路，以及分流器 电阻连接在地和功率元件的门之间。

公开(公告)号：US08586462B2

公开(公告)日：2013-11-19

申请号：US13307069

申请日：2011-11-30

申请人： Hokyun Ahn ,  Jong-Won Lim ,  Hyung Sup Yoon ,  Byoung-Gue Min ,  Sang-Heung Lee ,  Hae Cheon Kim ,  Eun Soo Nam

发明人： Hokyun Ahn ,  Jong-Won Lim ,  Hyung Sup Yoon ,  Byoung-Gue Min ,  Sang-Heung Lee ,  Hae Cheon Kim ,  Eun Soo Nam

IPC分类号： H01L29/808 ,  H01L21/283

CPC分类号： H01L29/7831 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/66863 ,  H01L29/7787 ,  H01L29/812

摘要： Disclosed are a method of manufacturing a field-effect transistor. The disclosed method includes: providing a semiconductor substrate; forming a source ohmic metal layer on one side of the semiconductor substrate; forming a drain ohmic metal layer on another side of the semiconductor substrate; forming a gate electrode between the source ohmic metal layer and the drain ohmic metal layer, on an upper portion of the semiconductor substrate; forming an insulating film on the semiconductor substrate's upper portion including the source ohmic metal layer, the drain ohmic metal layer and the gate electrode; and forming a plurality of field electrodes on an upper portion of the insulating film, wherein the insulating film below the respective field electrodes has different thicknesses.

摘要翻译： 公开了一种制造场效晶体管的方法。 所公开的方法包括：提供半导体衬底; 在半导体衬底的一侧上形成源极欧姆金属层; 在所述半导体衬底的另一侧上形成漏极欧姆金属层; 在所述源欧姆金属层和所述漏极欧姆金属层之间形成栅电极，在所述半导体衬底的上部; 在包括源欧姆金属层，漏极欧姆金属层和栅电极的半导体衬底的上部上形成绝缘膜; 以及在绝缘膜的上部形成多个场电极，其中各个场电极下方的绝缘膜具有不同的厚度。

公开(公告)号：US20110140175A1

公开(公告)日：2011-06-16

申请号：US12832432

申请日：2010-07-08

申请人： Byoung-Gue MIN ,  Jongmin Lee ,  Seong-ll Kim ,  Hyung Sup Yoon

发明人： Byoung-Gue MIN ,  Jongmin Lee ,  Seong-ll Kim ,  Hyung Sup Yoon

IPC分类号： H01L27/06 ,  H01L21/8222

CPC分类号： H01L29/66318 ,  H01L21/8252 ,  H01L27/0605 ,  H01L29/66204 ,  H01L29/7371 ,  H01L29/868

摘要： Provided are a monolithic microwave integrated circuit device and a method for forming the same. The method includes: forming an sub-collector layer, a collector layer, a base layer, an emitter layer, and an emitter cap layer on a Heterojunction Bipolar Transistor (HBT) region and a PIN diode region of a substrate; forming an emitter pattern and an emitter cap pattern in the HBT region and exposing the base layer by patterning the emitter layer and the emitter cap layer; and forming an intrinsic region by doping a portion of the collector layer of the PIN diode region with a first type impurity, the PIN diode region being spaced apart from the HBT region.

摘要翻译： 提供了一种单片微波集成电路器件及其形成方法。 该方法包括：在基底的异质结双极晶体管（HBT）区域和PIN二极管区域上形成子集电极层，集电极层，基极层，发射极层和发射极盖层; 在HBT区域中形成发射极图案和发射极盖图案，并通过图案化发射极层和发射极盖层而使基底层曝光; 并且通过用第一类型杂质掺杂PIN二极管区域的集电极层的一部分来形成本征区域，PIN二极管区域与HBT区域间隔开。

公开(公告)号：US20110133843A1

公开(公告)日：2011-06-09

申请号：US12960153

申请日：2010-12-03

申请人： Seong-Il KIM ,  Jongmin Lee ,  Byoung-Gue Min ,  Hyung Sup Yoon ,  Hae Cheon Kim ,  Eun Soo Nam

发明人： Seong-Il KIM ,  Jongmin Lee ,  Byoung-Gue Min ,  Hyung Sup Yoon ,  Hae Cheon Kim ,  Eun Soo Nam

IPC分类号： H03F3/68

CPC分类号： H03F3/245 ,  H03F1/0261 ,  H03F1/52 ,  H03F3/19 ,  H03F3/211 ,  H03F2200/18 ,  H03F2200/451

摘要： Provided is a power amplifier device. The power amplifier device includes: a cutoff unit cutting off a direct current (DC) component of a signal delivered from a signal input terminal; a circuit protecting unit connected to the cutoff unit and stabilizing a signal delivered from the cutoff unit; and an amplification unit connected to the circuit protecting unit and amplifying a signal delivered from the circuit protecting unit, wherein the amplification unit comprises a plurality of transistors connected in parallel to the circuit protecting unit and the circuit protecting unit comprises resistors connected to between bases of the plurality of transistors.

摘要翻译： 提供了一种功率放大器装置。 功率放大器装置包括：切断单元，切断从信号输入端子发送的信号的直流（DC）分量; 连接到所述切断单元的电路保护单元，并且稳定从所述切断单元传送的信号; 以及放大单元，连接到所述电路保护单元并放大从所述电路保护单元传递的信号，其中所述放大单元包括与所述电路保护单元并联连接的多个晶体管，所述电路保护单元包括电阻器， 多个晶体管。

公开(公告)号：US08338241B2

公开(公告)日：2012-12-25

申请号：US13283626

申请日：2011-10-28

申请人： Hyung Sup Yoon ,  Byoung-Gue Min ,  Hokyun Ahn ,  Sang-Heung Lee ,  Hae Cheon Kim

发明人： Hyung Sup Yoon ,  Byoung-Gue Min ,  Hokyun Ahn ,  Sang-Heung Lee ,  Hae Cheon Kim

IPC分类号： H01L21/338

CPC分类号： H01L29/7783 ,  H01L21/8252 ,  H01L27/0605 ,  H01L29/42316 ,  H01L29/66462

摘要： Provided are a method of manufacturing a normally-off mode high frequency device structure and a method of simultaneously manufacturing a normally-on mode high frequency device structure and a normally-off mode high frequency device structure on a single substrate.

摘要翻译： 提供一种制造常闭型高频器件结构的方法以及在单个衬底上同时制造常开模式高频器件结构和常关型高频器件结构的方法。

公开(公告)号：US20110140825A1

公开(公告)日：2011-06-16

申请号：US12968022

申请日：2010-12-14

申请人： Seong-il KIM ,  Jongmin Lee ,  Byoung-Gue Min ,  Hyung Sup Yoon ,  Hae Cheon Kim ,  Eun Soo Nam

发明人： Seong-il KIM ,  Jongmin Lee ,  Byoung-Gue Min ,  Hyung Sup Yoon ,  Hae Cheon Kim ,  Eun Soo Nam

IPC分类号： H01F27/30

CPC分类号： H01F17/0006 ,  H01F2017/0086 ,  H01L28/10

摘要： Provided is an inductor. The inductor includes a first to a fourth conductive terminals formed in one direction within a semiconductor substrate, a first conductive line formed on one side of the semiconductor substrate and electrically connected to the second and third conductive terminals interiorly positioned among the first to fourth conductive terminals, a second conductive line formed on the one side of the semiconductor substrate and electrically connected to the first and fourth conductive terminals exteriorly positioned among the first to fourth conductive terminals, and a third conductive line formed on the other side of the semiconductor substrate and electrically connected to the first and third conductive terminals among the first to fourth conductive terminals.

摘要翻译： 提供一种电感器。 电感器包括在半导体衬底内的一个方向上形成的第一至第四导电端子，形成在半导体衬底的一侧上的第一导电线，并且电连接到内部位于第一至第四导电端子之间的第二和第三导电端子 形成在所述半导体衬底的一侧上并与外部位于所述第一至第四导电端子之间的所述第一和第四导电端子电连接的第二导电线，以及形成在所述半导体衬底的另一侧上并电连接的第三导电线 连接到第一至第四导电端子中的第一和第三导电端子。