-
1.发明授权Method for improving visibility of alignment target in semiconductor processing 失效用于提高半导体处理中的对准目标的可见性的方法
公开(公告)号：US06015750A
公开(公告)日：2000-01-18
申请号：US7694
申请日：1998-01-15
IPC分类号： H01L23/544 , G01B11/27
CPC分类号： H01L23/544 , H01L2223/54453 , H01L2924/0002
摘要： Methods are disclosed that enhance the contrast between alignment targets and adjacent materials on a semiconductor wafer. According to a first embodiment, the TiN layer that is deposited during an earlier processing step is stripped away to enhance the reflectivity of the metal layer. According to a second embodiment, a reflective coating is added over the metal layer to enhance the reflectivity of the metal layer. According to a third embodiment, a reflective coating is added over the entire wafer to enhance the reflectivity of the metal layer. According to a fourth embodiment, an anti-reflective coating in a sandwich structure is added to reduce the reflectivity of the material adjacent the alignment targets. According to a fifth embodiment, an organic anti-reflective coating is added to reduce the reflectivity of the material adjacent the alignment targets. All of these embodiments result in a contrast between the alignment target and the adjacent material that is more consistent over variations in oxide thickness. The more uniform contrast makes it easier for the stepper system to identify the edges of the alignment targets, resulting in a more exact placement of the mask.
摘要翻译： 公开了增强半导体晶片上的对准目标和相邻材料之间的对比度的方法。 根据第一实施例，在较早处理步骤期间沉积的TiN层被剥离以增强金属层的反射率。 根据第二实施例，在金属层上添加反射涂层以增强金属层的反射率。 根据第三实施例，在整个晶片上添加反射涂层以增强金属层的反射率。 根据第四实施例，添加夹层结构中的抗反射涂层以降低邻近对准靶的材料的反射率。 根据第五实施例，添加有机抗反射涂层以降低邻近对准靶的材料的反射率。 所有这些实施例导致对准目标和相邻材料之间的对比度，其与氧化物厚度的变化更一致。 更均匀的对比度使得步进系统更容易识别对准目标的边缘，导致掩模更准确的放置。
-
2.发明授权Method for improving visibility of alignment targets in semiconductor processing 失效用于提高半导体处理中的对准目标的可见性的方法
公开(公告)号：US5760483A
公开(公告)日：1998-06-02
申请号：US772709
申请日：1996-12-23
IPC分类号： H01L23/544
CPC分类号： H01L23/544 , H01L2223/54453 , H01L2924/0002
摘要： Methods are disclosed that enhance the contrast between alignment targets and adjacent materials on a semiconductor wafer. According to a first embodiment, the TiN layer that is deposited during an earlier processing step is stripped away to enhance the reflectivity of the metal layer. According to a second embodiment, a reflective coating is added over the metal layer to enhance the reflectivity of the metal layer. According to a third embodiment, a reflective coating is added over the entire wafer to enhance the reflectivity of the metal layer. According to a fourth embodiment, an anti-reflective coating in a sandwich structure is added to reduce the reflectivity of the material adjacent the alignment targets. According to a fifth embodiment, an organic anti-reflective coating is added to reduce the reflectivity of the material adjacent the alignment targets. All of these embodiments result in a contrast between the alignment target and the adjacent material that is more consistent over variations in oxide thickness. The more uniform contrast makes it easier for the stepper system to identify the edges of the alignment targets, resulting in a more exact placement of the mask.
摘要翻译： 公开了增强半导体晶片上的对准目标和相邻材料之间的对比度的方法。 根据第一实施例，在较早处理步骤期间沉积的TiN层被剥离以增强金属层的反射率。 根据第二实施例，在金属层上添加反射涂层以增强金属层的反射率。 根据第三实施例，在整个晶片上添加反射涂层以增强金属层的反射率。 根据第四实施例，添加夹层结构中的抗反射涂层以降低邻近对准靶的材料的反射率。 根据第五实施例，添加有机抗反射涂层以降低邻近对准靶的材料的反射率。 所有这些实施例导致对准目标和相邻材料之间的对比度，其与氧化物厚度的变化更一致。 更均匀的对比度使得步进系统更容易识别对准目标的边缘，导致掩模更准确的放置。
-
3.发明授权Method of photolithographically defining three regions with one mask step and self aligned isolation structure formed thereby 失效用一个掩模步骤和由此形成的自对准隔离结构光刻地限定三个区域的方法
公开(公告)号：US6147394A
公开(公告)日：2000-11-14
申请号：US172366
申请日：1998-10-14
IPC分类号： G03F7/004 , G03F1/00 , G03F7/095 , G03F7/20 , H01L21/027 , H01L21/302 , H01L21/3065 , H01L21/76 , H01L21/762 , H01L29/00
CPC分类号： G03F7/70633 , G03F7/095 , G03F7/2022 , G03F7/2024 , H01L21/0274 , H01L21/762
摘要： The preferred embodiment of the present invention provides a method for defining three regions on a semiconductor substrate using a single masking step. The preferred embodiment uses a photoresist material having, simultaneously, both a positive tone and a negative tone response to exposure. This combination of materials can provide a new type of resist, which we call a hybrid resist. The hybrid resist comprises a positive tone component which acts at a first actinic energy level and a negative tone component which acts at a second actinic energy level, with the first and second actinic energy levels being separated by an intermediate range of actinic energy. When hybrid resist is exposed to actinic energy, areas of the resist which are subject to a full exposure cross link to form a negative tone line pattern, areas which are unexposed form remain photoactive and form a positive tone pattern, and areas which are exposed to intermediate amounts of radiation become soluble and wash away during development. This exposes a first region on the mask. By then blanket exposing the hybrid resist, the positive tone patterns become soluble and will wash away during development. This exposes a second region on the mask, with the third region still be covered by the hybrid resist. Thus, the preferred embodiment is able to define three regions using a single masking step, with no chance for overlay errors.
摘要翻译： 本发明的优选实施例提供了一种使用单个掩蔽步骤在半导体衬底上限定三个区域的方法。 优选实施例使用光刻胶材料，同时具有曝光的正色调和负色调响应。 这种材料的组合可以提供一种新型的抗蚀剂，我们称之为混合抗蚀剂。 混合抗蚀剂包含作用于第一光化能级的正色调成分和以第二光化能级起作用的负色调成分，其中第一和第二光化能级被光化能的中间范围分隔。 当混合抗蚀剂暴露于光化能时，受到完全曝光的抗蚀剂的区域交联以形成负色调线图案，未曝光形式的区域保持光活性并形成正色调图案，并且暴露于 中间量的辐射在开发过程中变得可溶并被冲走。 这暴露了掩码上的第一个区域。 然后毯子暴露混合抗蚀剂，正色调图案变得可溶，并且在显影过程中将被洗掉。 这掩盖了掩模上的第二区域，第三区域仍被混合抗蚀剂覆盖。 因此，优选实施例能够使用单个掩蔽步骤来定义三个区域，而不会叠加错误。
-
公开(公告)号：US5972570A
公开(公告)日：1999-10-26
申请号：US895748
申请日：1997-07-17
IPC分类号： G03F7/004 , G03F1/00 , G03F7/095 , G03F7/20 , H01L21/027 , H01L21/302 , H01L21/3065 , H01L21/76 , H01L21/762 , G03F7/26
CPC分类号： G03F7/70633 , G03F7/095 , G03F7/2022 , G03F7/2024 , H01L21/0274 , H01L21/762
摘要： The preferred embodiment of the present invention provides a method for defining three regions on a semiconductor substrate using a single masking step. The preferred embodiment uses a photoresist material having, simultaneously, both a positive tone and a negative tone response to exposure. This combination of materials can provide a new type of resist, which we call a hybrid resist. The hybrid resist comprises a positive tone component which acts at a first actinic energy level and a negative tone component which acts at a second actinic energy level, with the first and second actinic energy levels being separated by an intermediate range of actinic energy. When hybrid resist is exposed to actinic energy, areas of the resist which are subject to a full exposure cross link to form a negative tone line pattern, areas which are unexposed form remain photoactive and form a positive tone pattern, and areas which are exposed to intermediate amounts of radiation become soluble and wash away during development. This exposes a first region on the mask. By then blanket exposing the hybrid resist, the positive tone patterns become soluble and will wash away during development. This exposes a second region on the mask, with the third region still be covered by the hybrid resist. Thus, the preferred embodiment is able to define three regions using a single masking step, with no chance for overlay errors.
-
公开(公告)号：US5552718A
公开(公告)日：1996-09-03
申请号：US368181
申请日：1995-01-04
IPC分类号： G01R31/26
CPC分类号： G01R31/26
摘要： This describes a test pattern and method for measuring dimensional characteristics of features formed on a surface. This is realized and provided by forming a space, defined by the feature, in intersecting relationship with a pair of conductive lines of a test pattern configuration such that the lines are altered at the intersection with the space in accordance with the dimensions of that space, measuring the resistance of at least one of the lines in a region remote from the intersection with the space and the resistance of each line in the region of its intersection with the space, and comparing the resistance of the remote region with the resistances for the region of each of the lines where they intersect the space to thereby establish the position of, and at least one dimension of that space. A test structure wherein the spaced lines intersect the longitudinal ends of the space is utilized for determining the length and the longitudinal position of the space, and a test structure where lines intersect the lateral edges of the space is utilized for determining the width of and the lateral position of the space. For measuring the dimensional characteristics of a line feature, the above noted patterns are utilized, after first replicating the line as a space.
摘要翻译： 这描述了用于测量在表面上形成的特征的尺寸特性的测试图案和方法。 这通过以与测试图案配置的一对导线相交的方式形成由特征限定的空间来实现并提供，使得根据该空间的尺寸在与空间的交叉处改变线， 测量远离与该空间相交的区域的空间和电阻的区域中的至少一条线路的电阻，并将该偏移区域的电阻与该区域的电阻进行比较 其中它们与空间相交的每条线，从而建立该空间的位置和至少一个维度。 用于确定空间的长度和纵向位置的测量结构，其中与空间的纵向端部相交的间隔线用于确定空间的横向边缘的线和与该空间的横向边缘相交的测试结构， 横向位置的空间。 为了测量线特征的尺寸特征，在首先将线复制为空间之后，利用上述图案。
-
公开(公告)号：US08753917B2
公开(公告)日：2014-06-17
申请号：US12967625
申请日：2010-12-14
IPC分类号： H01L31/112
CPC分类号： H01L31/105 , H01L27/14632 , H01L27/14636 , H01L27/14665 , H01L27/14687
摘要： A design structure embodied in a machine readable medium used in a design process includes a first dielectric layer disposed on an intermediary layer, a first conductive pad portion and a first interconnect portion disposed on the first dielectric layer, a second dielectric layer disposed on the first dielectric layer, a first capping layer disposed on the first interconnect portion and a portion of the first conductive pad portion, a second capping layer disposed on the first capping layer and a portion of the second dielectric layer, an n-type doped silicon layer disposed on the second capping layer and the first conductive pad portion, an intrinsic silicon layer disposed on the n-type doped silicon layer, and a p-type doped silicon layer disposed on the intrinsic silicon layer.
摘要翻译： 体现在设计过程中使用的机器可读介质中的设计结构包括设置在中间层上的第一介电层，设置在第一介电层上的第一导电焊盘部分和第一互连部分，设置在第一介电层上的第二介电层 电介质层，设置在第一互连部分上的第一覆盖层和第一导电焊盘部分的一部分，设置在第一覆盖层上的第二封盖层和第二介电层的一部分，设置n型掺杂硅层 在第二覆盖层和第一导电焊盘部分上，设置在n型掺杂硅层上的本征硅层和设置在本征硅层上的p型掺杂硅层。
-
7.发明授权Resized wafer with a negative photoresist ring and design structures thereof 有权具有负光致抗蚀剂环的尺寸调整晶片及其设计结构公开(公告)号：US08536025B2
公开(公告)日：2013-09-17
申请号：US13316978
申请日：2011-12-12
IPC分类号： H01L21/46 , H01L21/301
CPC分类号： H01L21/76838 , H01L21/302 , H01L21/3083
摘要： A resized wafer using a negative photoresist ring, methods of manufacture and design structures thereof are disclosed. The method includes forming a ring within a radius of a wafer. The method also includes patterning a photoresist formed on the wafer, by exposing the photoresist to energy. Additionally, the method includes forming troughs in a substrate of the wafer based on the patterning of the photoresist, wherein the ring blocks formation of the troughs underneath the ring. The method also includes filling the troughs with a metal and resizing the wafer at an area of the ring.
摘要翻译： 公开了使用负型光致抗蚀剂环的尺寸调整的晶片，其制造方法和设计结构。 该方法包括在晶片的半径内形成环。 该方法还包括通过将光致抗蚀剂暴露于能量来图案化形成在晶片上的光致抗蚀剂。 另外，该方法包括基于光刻胶的图案形成在晶片的衬底中形成槽，其中环阻挡环下方的槽的形成。 该方法还包括用金属填充槽并且在环的区域上调整晶片大小。
-
8.发明授权Apparatus for real-time contamination, environmental, or physical monitoring of a photomask 有权用于光掩模的实时污染，环境或物理监测的装置公开(公告)号：US07929117B2
公开(公告)日：2011-04-19
申请号：US12056047
申请日：2008-03-26
CPC分类号： G03F1/84 , G03F7/7085 , G03F7/70875 , G03F7/709 , G03F7/70916 , G03F7/70983
摘要： An apparatus for real-time contamination, environmental, or physical monitoring of a photomask. The apparatus includes a photomask having a patterned region configured to correspond to features of an integrated circuit and a sensor physically coupled with the photomask. The sensor is configured to monitor an attribute related to the photomask. Attributes monitored by the sensor may include chemical contamination, temperature changes, humidity changes, acceleration, shock, vibration, optical flux through the photomask, electrostatic discharge environment of the photomask, particulates, and pressure.
摘要翻译： 一种用于光掩模的实时污染，环境或物理监测的设备。 该装置包括光掩模，其具有被配置为对应于集成电路的特征的图案区域和与光掩模物理耦合的传感器。 传感器被配置为监视与光掩模相关的属性。 由传感器监测的属性可能包括化学污染，温度变化，湿度变化，加速度，冲击，振动，通过光掩模的光通量，光掩模的静电放电环境，微粒和压力。
-
公开(公告)号：US07707535B2
公开(公告)日：2010-04-27
申请号：US11849461
申请日：2007-09-04
申请人： Timothy G. Dunham , Robert K. Leidy , Kevin N. Ogg , Richard J. Rassel , Valarmathi C. Shanmugam
发明人： Timothy G. Dunham , Robert K. Leidy , Kevin N. Ogg , Richard J. Rassel , Valarmathi C. Shanmugam
IPC分类号： G06F17/50
CPC分类号： G03F7/70475 , G03F7/70466 , G03F7/70691
摘要： Stitched integrated circuit (IC) chip layout design structures are disclosed. In one embodiment, a design structure embodied in a machine readable medium used in a design process includes: an integrated circuit (IC) chip layout exceeding a size of a photolithography tool field, the IC chip layout including: a plurality of stitched regions including at least one redundant stitched region or at least one unique stitched region; and for each stitched region: a boundary identification identifying a boundary of the stitched region at which stitching occurs.
摘要翻译： 公开了拼接集成电路（IC）芯片布局设计结构。 在一个实施例中，在设计过程中使用的机器可读介质中体现的设计结构包括：超过光刻工具领域尺寸的集成电路（IC）芯片布局，所述IC芯片布局包括：多个缝合区域， 至少一个冗余缝合区域或至少一个独特的缝合区域; 并且针对每个缝合区域：识别发生缝合的缝合区域的边界的边界标识。
-
10.发明申请公开(公告)号：US20100031223A1
公开(公告)日：2010-02-04
申请号：US12182672
申请日：2008-07-30
IPC分类号： G06F17/50
CPC分类号： G03F7/70916 , G03F7/70525 , G03F7/70741 , G03F7/7085 , G03F7/70991
摘要： Systems for real-time contamination, environmental, or physical monitoring of a photomask. The system includes an electronics package physically mounted to the photomask and a processing device in communication with the electronics package. The electronics package includes a sensor configured to monitor the attribute and generate sensor data. The processing device is configured to analyze the sensor data communicated from the electronics package to the processing device.
摘要翻译： 用于光掩模的实时污染，环境或物理监测的系统。 该系统包括物理地安装到光掩模的电子封装以及与电子封装通信的处理装置。 电子组件包括配置成监视属性并生成传感器数据的传感器。 处理装置被配置为分析从电子包装传送到处理装置的传感器数据。
-
-
-
-
-
-
-
-
-
搜索结果
96 条记录 (耗时 0.024 秒)