公开(公告)号：US20060110905A1

公开(公告)日：2006-05-25

申请号：US10904677

申请日：2004-11-23

申请人： James Adkisson ,  Jeffrey Gambino ,  Mark Jaffe ,  Richard Rassel ,  Edmund Sprogis

发明人： James Adkisson ,  Jeffrey Gambino ,  Mark Jaffe ,  Richard Rassel ,  Edmund Sprogis

IPC分类号： H01L21/44 ,  H01L21/50

CPC分类号： H01L24/02 ,  H01L23/3114 ,  H01L23/481 ,  H01L2224/0401 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/3011 ,  H01L2924/00

摘要： A bond pad for effecting through-wafer connections to an integrated circuit or electronic package and method of producing thereof. The bond pad includes a high surface area aluminum bond pad in order to resultingly obtain a highly reliable, low resistance connection between bond pad and electrical leads.

摘要翻译： 用于实现通过晶片连接到集成电路或电子封装的接合焊盘及其制造方法。 接合焊盘包括高表面积铝键合焊盘，以便得到接合焊盘和电引线之间的高度可靠的低电阻连接。

公开(公告)号：US20080073742A1

公开(公告)日：2008-03-27

申请号：US11943277

申请日：2007-11-20

申请人： James Adkisson ,  Jeffrey Gambino ,  Mark Jaffe ,  Robert Leidy ,  Stephen Luce ,  Richard Rassell ,  Edmund Sprogis

发明人： James Adkisson ,  Jeffrey Gambino ,  Mark Jaffe ,  Robert Leidy ,  Stephen Luce ,  Richard Rassell ,  Edmund Sprogis

IPC分类号： H01L31/00 ,  H01L21/98

CPC分类号： H01L27/14618 ,  H01L25/0657 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/13091 ,  H01L2924/15151 ,  H01L2924/00014 ,  H01L2924/00

摘要： An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the imaging chip. The backside metallurgy of the imaging chip is connected to metallurgy on the active surface of the logic chip using an array of solder bumps in BGA fashion. The interconnection arrangement provides a CSP which matches the space constraints of a cell phone, for example. The arrangement also utilizes minimal wire lengths for reduced noise. Connection of the CSP to a carrier package may be either by conductive through vias or wire bonding. The CSP is such that the imaging chip may readily be mounted across an aperture in the wall of a cell phone, for example, so as to expose the light sensitive pixels on the active surface of said imaging chip to light.

摘要翻译： 用于数码相机或手机的成像系统利用一个芯片用于逻辑和一个芯片用于图像处理。 这些芯片使用围绕成像芯片的有源表面上的接合焊盘的边缘或通孔导体互连，从而在成像芯片上进行背面冶金。 成像芯片的背面冶金采用BGA焊料凸块阵列与逻辑芯片的有源表面上的冶金连接。 互连装置提供例如与手机的空间限制相匹配的CSP。 该布置还利用最小的线长度来降低噪声。 将CSP连接到载体封装可以通过通孔或引线键合导电。 CSP使得成像芯片可以容易地安装在例如手机的壁中的孔之间，以便将所述成像芯片的有效表面上的光敏像素曝光到光。

公开(公告)号：US20080108170A1

公开(公告)日：2008-05-08

申请号：US11959841

申请日：2007-12-19

申请人： James Adkisson ,  Jeffrey Gambino ,  Mark Jaffe ,  Robert Leidy ,  Richard Rassel ,  Anthony Stamper

发明人： James Adkisson ,  Jeffrey Gambino ,  Mark Jaffe ,  Robert Leidy ,  Richard Rassel ,  Anthony Stamper

IPC分类号： H01L21/04

CPC分类号： H01L27/14636 ,  H01L21/76819 ,  H01L21/76834 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/14645 ,  H01L27/14683

摘要： A CMOS image sensor and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack to result in a pixel array exhibiting increased light sensitivity. The CMOS image sensor includes structures having a minimum thickness of barrier layer metal that traverses the optical path of each pixel in the sensor array or, that have portions of barrier layer metal selectively removed from the optical paths of each pixel, thereby minimizing reflectance. That is, by implementing various block or single mask methodologies, portions of the barrier layer metal are completely removed at locations of the optical path for each pixel in the array. In a further embodiment, the barrier metal layer may be formed atop the Cu metallization by a self-aligned deposition.

摘要翻译： CMOS图像传感器和制造方法，其中传感器包括铜（Cu）金属化水平，允许结合较薄的层间电介质堆叠以产生呈现增加的光灵敏度的像素阵列。 CMOS图像传感器包括具有穿过传感器阵列中的每个像素的光路的阻挡层金属的最小厚度的结构，或者具有从每个像素的光路中选择性地去除的阻挡层金属的部分，从而使反射率最小化的结构。 也就是说，通过实现各种块或单掩模方法，在阵列中的每个像素的光路的位置处完全去除了阻挡层金属的部分。 在另一个实施例中，阻挡金属层可以通过自对准沉积形成在Cu金属化之上。

公开(公告)号：US20070194397A1

公开(公告)日：2007-08-23

申请号：US11276218

申请日：2006-02-17

申请人： James Adkisson ,  Jeffrey Gambino ,  Mark Jaffe ,  Alan Loiseau ,  Richard Rassel

发明人： James Adkisson ,  Jeffrey Gambino ,  Mark Jaffe ,  Alan Loiseau ,  Richard Rassel

IPC分类号： H01L31/0232 ,  H01L31/00

CPC分类号： H01L27/14643 ,  H01L27/14621 ,  H01L27/1463 ,  H01L27/1464 ,  H01L27/14689

摘要： An imaging sensor with an array of FET pixels and method of forming the imaging sensor. Each pixel is a semiconductor island, e.g., N-type silicon on a Silicon on insulator (SOI) wafer. FETs are formed in one photodiode electrode, e.g., a P-well cathode. A color filter may be attached to an opposite surface of island. A protective layer (e.g., glass or quartz) or window is fixed to the pixel array at the color filters. The image sensor may be illuminated from the backside with cell wiring above the cell. So, an optical signal passes through the protective layer is filtered by the color filters and selectively sensed by a corresponding photo-sensor.

摘要翻译： 具有FET像素阵列的成像传感器和形成成像传感器的方法。 每个像素是半导体岛，例如绝缘体上硅（SOI）晶片上的N型硅。 FET形成在一个光电二极管电极中，例如P阱阴极。 滤色器可以附接到岛的相对表面。 保护层（例如，玻璃或石英）或窗口在滤色器处固定到像素阵列。 图像传感器可以从背面照亮，电池布线在电池单元上方。 因此，通过保护层的光学信号被滤色器过滤并被相应的光电传感器选择性地感测。

公开(公告)号：US20060186505A1

公开(公告)日：2006-08-24

申请号：US10906510

申请日：2005-02-23

申请人： James Adkisson ,  John Ellis-Monaghan ,  Jeffrey Gambino ,  Mark Jaffe ,  Richard Rassel

发明人： James Adkisson ,  John Ellis-Monaghan ,  Jeffrey Gambino ,  Mark Jaffe ,  Richard Rassel

IPC分类号： H01L31/06

CPC分类号： H01L27/14609 ,  H01L27/1463 ,  H01L27/14641 ,  H01L27/14643 ,  H01L31/035281

摘要： A structure (and method for forming the same) for an image sensor cell. The structure includes (a) a semiconductor substrate; (b) a charge collection well on the substrate, the charge collection well comprising a semiconductor material doped with a first doping polarity; (c) a surface pinning layer on and in direct physical contact with the charge collection well, the surface pinning layer comprising a semiconductor material doped with a second doping polarity opposite to the first doping polarity; and (d) an electrically conducting push electrode being in direct physical contact with the surface pinning layer but not being in direct physical contact with the charge collection well.

摘要翻译： 用于图像传感器单元的结构（及其形成方法）。 该结构包括（a）半导体衬底; （b）在所述衬底上的电荷收集阱，所述电荷收集阱包括掺杂有第一掺杂极性的半导体材料; （c）与电荷收集阱直接物理接触的表面钉扎层，所述表面钉扎层包括掺杂有与第一掺杂极性相反的第二掺杂极性的半导体材料; 和（d）与表面钉扎层直接物理接触但不与电荷收集阱直接物理接触的导电推动电极。

公开(公告)号：US20060138480A1

公开(公告)日：2006-06-29

申请号：US10905277

申请日：2004-12-23

申请人： James Adkisson ,  Jeffrey Gambino ,  Mark Jaffe ,  Robert Leidy ,  Richard Rassel ,  Anthony Stamper

发明人： James Adkisson ,  Jeffrey Gambino ,  Mark Jaffe ,  Robert Leidy ,  Richard Rassel ,  Anthony Stamper

IPC分类号： H01L31/113 ,  H01L31/0232 ,  H01L31/00

CPC分类号： H01L27/14636 ,  H01L21/76819 ,  H01L21/76834 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/14645 ,  H01L27/14683

摘要： An image sensor and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack to result in a pixel array exhibiting increased light sensitivity. The image sensor includes structures having a minimum thickness of barrier layer metal that traverses the optical path of each pixel in the sensor array or, that have portions of barrier layer metal selectively removed from the optical paths of each pixel, thereby minimizing reflectance. That is, by implementing various block or single mask methodologies, portions of the barrier layer metal are completely removed at locations of the optical path for each pixel in the array. In a further embodiment, the barrier metal layer may be formed atop the Cu metallization by a self-aligned deposition.

摘要翻译： 一种图像传感器和制造方法，其中传感器包括铜（Cu）金属化水平，允许结合较薄的层间电介质堆叠以产生呈现增加的光敏度的像素阵列。 图像传感器包括具有穿过传感器阵列中的每个像素的光路的阻挡层金属的最小厚度的结构，或者具有从每个像素的光路中选择性地去除的阻挡层金属的部分，从而使反射率最小化。 也就是说，通过实现各种块或单掩模方法，在阵列中的每个像素的光路的位置处完全去除了阻挡层金属的部分。 在另一个实施例中，阻挡金属层可以通过自对准沉积形成在Cu金属化之上。

公开(公告)号：US20070158711A1

公开(公告)日：2007-07-12

申请号：US11275497

申请日：2006-01-10

申请人： James Adkisson ,  Jeffrey Gambino ,  Mark Jaffe ,  Jeffrey Johnson ,  Jerome Lasky ,  Richard Rassel

发明人： James Adkisson ,  Jeffrey Gambino ,  Mark Jaffe ,  Jeffrey Johnson ,  Jerome Lasky ,  Richard Rassel

IPC分类号： H01L31/113 ,  H01L27/148 ,  H01L29/768

CPC分类号： H01L27/1462 ,  H01L27/14603 ,  H01L27/1463

摘要： Structures and method for forming the same. The semiconductor structure comprises a photo diode that includes a first semiconductor region and a second semiconductor region. The first and second semiconductor regions are doped with a first and second doping polarities, respectively, and the first and second doping polarities are opposite. The semiconductor structure also comprises a transfer gate that comprises (i) a first extension region, (ii) a second extension region, and (iii) a floating diffusion region. The first and second extension regions are in direct physical contact with the photo diode and the floating diffusion region, respectively. The semiconductor structure further comprises a charge pushing region. The charge pushing region overlaps the first semiconductor region and does not overlap the floating diffusion region. The charge pushing region comprises a transparent and electrically conducting material.

摘要翻译： 结构及其形成方法。 该半导体结构包括包含第一半导体区域和第二半导体区域的光电二极管。 第一和第二半导体区域分别掺杂有第一和第二掺杂极性，并且第一和第二掺杂极性相反。 半导体结构还包括传输门，其包括（i）第一延伸区，（ii）第二延伸区和（iii）浮动扩散区。 第一和第二延伸区分别与光电二极管和浮动扩散区直接物理接触。 半导体结构还包括电荷推送区域。 电荷推送区域与第一半导体区域重叠，并且不与浮动扩散区域重叠。 电荷推送区域包括透明且导电的材料。

公开(公告)号：US20070108485A1

公开(公告)日：2007-05-17

申请号：US11619024

申请日：2007-01-02

申请人： James Adkisson ,  John Ellis-Monaghan ,  Jeffrey Gambino ,  Mark Jaffe ,  Richard Rassel

发明人： James Adkisson ,  John Ellis-Monaghan ,  Jeffrey Gambino ,  Mark Jaffe ,  Richard Rassel

IPC分类号： H01L31/113 ,  H01L21/00

CPC分类号： H01L27/14609 ,  H01L27/1463 ,  H01L27/14641 ,  H01L27/14643 ,  H01L31/035281

摘要： A structure (and method for forming the same) for an image sensor cell. The method includes providing a semiconductor substrate. Then, a charge collection well is formed in the semiconductor substrate, the charge collection well comprising dopants of a first doping polarity. Next, a surface pinning layer is formed in the charge collection well, the surface pinning layer comprising dopants of a second doping polarity opposite to the first doping polarity. Then, an electrically conductive push electrode is formed in direct physical contact with the surface pinning layer but not in direct physical contact with the charge collection well. Then, a transfer transistor is formed on the semiconductor substrate. The transfer transistor includes first and second source/drain regions and a channel region. The first and second source/drain regions comprise dopants of the first doping polarity. The first source/drain region is in direct physical contact with the charge collection well.

摘要翻译： 用于图像传感器单元的结构（及其形成方法）。 该方法包括提供半导体衬底。 然后，在半导体衬底中形成电荷收集阱，电荷收集阱包含第一掺杂极性的掺杂剂。 接下来，在电荷收集阱中形成表面钉扎层，表面钉扎层包括与第一掺杂极性相反的第二掺杂极性的掺杂剂。 然后，导电的推动电极形成为与表面钉扎层直接物理接触，但不与电荷收集阱直接物理接触。 然后，在半导体衬底上形成传输晶体管。 传输晶体管包括第一和第二源极/漏极区域和沟道区域。 第一和第二源/漏区包括第一掺杂极性的掺杂剂。 第一源极/漏极区域与电荷收集阱直接物理接触。

公开(公告)号：US20070138380A1

公开(公告)日：2007-06-21

申请号：US11275171

申请日：2005-12-16

申请人： James Adkisson ,  Jeffrey Gambino ,  Robert Leidy ,  Richard Rassel

发明人： James Adkisson ,  Jeffrey Gambino ,  Robert Leidy ,  Richard Rassel

IPC分类号： G01J1/04

CPC分类号： G01J1/04 ,  G01J1/0407 ,  G01J1/0422 ,  G01J1/0488

摘要： A photo sensing structure and methods for forming the same. The structure includes (a) a semiconductor substrate and (b) a photo collection region on the semiconductor substrate. The structure also includes a funneled light pipe on top of the photo collection region. The funneled light pipe includes (i) a bottom cylindrical portion on top of the photo collection region of the photo collection region, and (ii) a funneled portion which has a tapered shape and is on top and in direct physical contact with the bottom cylindrical portion. The structure further includes a color filter region on top of the funneled light pipe.

摘要翻译： 感光结构及其形成方法。 该结构包括（a）半导体衬底和（b）半导体衬底上的光收集区域。 该结构还包括在照片收集区域顶部的漏斗光管。 漏斗式光管包括（i）照片收集区域的照片收集区域顶部的底部圆柱形部分，和（ii）具有锥形形状并且在顶部并与底部圆柱体直接物理接触的漏斗部分 一部分。 该结构还包括在漏斗的光管的顶部上的滤色器区域。

公开(公告)号：US20070262305A1

公开(公告)日：2007-11-15

申请号：US11382492

申请日：2006-05-10

申请人： James Adkisson ,  Jeffrey Gambino ,  Richard Rassel ,  Steven Voldman

发明人： James Adkisson ,  Jeffrey Gambino ,  Richard Rassel ,  Steven Voldman

IPC分类号： H01L23/58

CPC分类号： H01L23/60 ,  H01L22/32 ,  H01L27/0248 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit wafer containing a plurality of integrated circuit chips and having a common substrate, each chip formed with an internal region in the interior of the chip and a removable external region on the perimeter of the internal region and circuitry disposed preferably in the external region and connected to at least one pad of an integrated circuit chip and the wafer substrate to establish electrical connection during electrostatic discharge and prevent ESD damage. The pad and substrate are isolated during tested of the integrated circuit chips in the wafer. Preferably, the external region is removed when the integrated circuit chips are diced from the wafer.

摘要翻译： 一种包含多个集成电路芯片并具有公共基板的半导体集成电路晶片，每个芯片在芯片的内部形成有内部区域，并且在内部区域的周边上具有可移除的外部区域，优选地设置在外部 并且连接到集成电路芯片的至少一个焊盘和晶片衬底，以在静电放电期间建立电连接并防止ESD损坏。 在晶片中的集成电路芯片的测试期间隔离衬垫和衬底。 优选地，当从晶片切割集成电路芯片时，去除外部区域。