公开(公告)号：US20060110905A1

公开(公告)日：2006-05-25

申请号：US10904677

申请日：2004-11-23

申请人： James Adkisson ,  Jeffrey Gambino ,  Mark Jaffe ,  Richard Rassel ,  Edmund Sprogis

发明人： James Adkisson ,  Jeffrey Gambino ,  Mark Jaffe ,  Richard Rassel ,  Edmund Sprogis

IPC分类号： H01L21/44 ,  H01L21/50

CPC分类号： H01L24/02 ,  H01L23/3114 ,  H01L23/481 ,  H01L2224/0401 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/3011 ,  H01L2924/00

摘要： A bond pad for effecting through-wafer connections to an integrated circuit or electronic package and method of producing thereof. The bond pad includes a high surface area aluminum bond pad in order to resultingly obtain a highly reliable, low resistance connection between bond pad and electrical leads.

摘要翻译： 用于实现通过晶片连接到集成电路或电子封装的接合焊盘及其制造方法。 接合焊盘包括高表面积铝键合焊盘，以便得到接合焊盘和电引线之间的高度可靠的低电阻连接。

公开(公告)号：US20080073742A1

公开(公告)日：2008-03-27

申请号：US11943277

申请日：2007-11-20

申请人： James Adkisson ,  Jeffrey Gambino ,  Mark Jaffe ,  Robert Leidy ,  Stephen Luce ,  Richard Rassell ,  Edmund Sprogis

发明人： James Adkisson ,  Jeffrey Gambino ,  Mark Jaffe ,  Robert Leidy ,  Stephen Luce ,  Richard Rassell ,  Edmund Sprogis

IPC分类号： H01L31/00 ,  H01L21/98

CPC分类号： H01L27/14618 ,  H01L25/0657 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/13091 ,  H01L2924/15151 ,  H01L2924/00014 ,  H01L2924/00

摘要： An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the imaging chip. The backside metallurgy of the imaging chip is connected to metallurgy on the active surface of the logic chip using an array of solder bumps in BGA fashion. The interconnection arrangement provides a CSP which matches the space constraints of a cell phone, for example. The arrangement also utilizes minimal wire lengths for reduced noise. Connection of the CSP to a carrier package may be either by conductive through vias or wire bonding. The CSP is such that the imaging chip may readily be mounted across an aperture in the wall of a cell phone, for example, so as to expose the light sensitive pixels on the active surface of said imaging chip to light.

摘要翻译： 用于数码相机或手机的成像系统利用一个芯片用于逻辑和一个芯片用于图像处理。 这些芯片使用围绕成像芯片的有源表面上的接合焊盘的边缘或通孔导体互连，从而在成像芯片上进行背面冶金。 成像芯片的背面冶金采用BGA焊料凸块阵列与逻辑芯片的有源表面上的冶金连接。 互连装置提供例如与手机的空间限制相匹配的CSP。 该布置还利用最小的线长度来降低噪声。 将CSP连接到载体封装可以通过通孔或引线键合导电。 CSP使得成像芯片可以容易地安装在例如手机的壁中的孔之间，以便将所述成像芯片的有效表面上的光敏像素曝光到光。

公开(公告)号：US20070132067A1

公开(公告)日：2007-06-14

申请号：US11557668

申请日：2006-11-08

申请人： Timothy Dalton ,  Jeffrey Gambino ,  Mark Jaffe ,  Stephen Luce ,  Edmund Sprogis

发明人： Timothy Dalton ,  Jeffrey Gambino ,  Mark Jaffe ,  Stephen Luce ,  Edmund Sprogis

IPC分类号： H01L23/544

CPC分类号： H01L23/544 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/54453 ,  H01L2225/06513 ,  H01L2225/06531 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/00

摘要： Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The first and second semiconductor wafers are in direct physical contact with each other via a common surface. If the first and second semiconductor wafers are moved with respect to each other by a first displacement distance of 1 nm in a first direction while the first and second semiconductor wafers are in direct physical contact with each other via the common surface, then a change of at least 10−18 F in capacitance of a first capacitor comprising the first and second capacitive coupling structures results. The first direction is essentially parallel to the common surface.

摘要翻译： 用于对准晶片的结构及其操作方法。 该结构包括（a）包括第一电容耦合结构的第一半导体晶片和（b）包括第二电容耦合结构的第二半导体晶片。 第一和第二半导体晶片经由公共表面彼此直接物理接触。 如果第一和第二半导体晶片在第一方向上相对于彼此移动了1nm的第一位移距离，同时第一和第二半导体晶片经由公共表面彼此直接物理接触，则 包括第一电容耦合结构和第二电容耦合结构的第一电容器的电容中的至少10 -18 F。 第一个方向基本上平行于共同的表面。

公开(公告)号：US20060246703A1

公开(公告)日：2006-11-02

申请号：US10908084

申请日：2005-04-27

申请人： Timothy Daubenspeck ,  Jeffrey Gambino ,  Christopher Muzzy ,  Wolfgang Sauter ,  Edmund Sprogis

发明人： Timothy Daubenspeck ,  Jeffrey Gambino ,  Christopher Muzzy ,  Wolfgang Sauter ,  Edmund Sprogis

IPC分类号： H01L21/44

CPC分类号： H01L23/556 ,  H01L24/02 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/00 ,  H01L2924/00014

摘要： A structure and a method for forming the same. The method includes (a) providing a structure which includes (i) a dielectric layer, (ii) an electrically conducting bond pad on and in direct physical contact with the dielectric layer top surface, (iii) a first passivation layer on the dielectric layer top surface and on the electrically conducting bond pad, wherein the first passivation layer comprises a first hole directly above the electrically conducting bond pad, and (iv) an electrically conducting solder bump filling the first hole and electrically coupled to the electrically conducting bond pad; and (b) forming a second passivation layer on the first passivation layer, wherein second passivation layer is in direct physical contact with the electrically conducting solder bump, and wherein the electrically conducting solder bump is exposed to a surrounding ambient immediately after said forming the second passivation layer is performed.

摘要翻译： 一种结构及其形成方法。 该方法包括（a）提供一种结构，其包括（i）电介质层，（ii）与电介质层顶表面直接物理接触的导电接合焊盘，（iii）介电层上的第一钝化层 其中所述第一钝化层包括位于所述导电接合焊盘正上方的第一孔，以及（iv）填充所述第一孔并电耦合到所述导电接合焊盘的导电焊料凸块; 以及（b）在所述第一钝化层上形成第二钝化层，其中第二钝化层与所述导电焊料凸块直接物理接触，并且其中所述导电焊料凸点在所述第二钝化层形成所述第二钝化层之后立即暴露于周围环境 执行钝化层。

公开(公告)号：US20090065925A1

公开(公告)日：2009-03-12

申请号：US12186655

申请日：2008-08-06

申请人： Kerry Bernstein ,  Timothy Dalton ,  Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Christopher David Muzzy ,  Wolfgang Sauter ,  Edmund Sprogis ,  Anthony Kendall Stamper

发明人： Kerry Bernstein ,  Timothy Dalton ,  Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Christopher David Muzzy ,  Wolfgang Sauter ,  Edmund Sprogis ,  Anthony Kendall Stamper

IPC分类号： H01L23/48

CPC分类号： H01L24/10 ,  H01L23/13 ,  H01L23/481 ,  H01L23/49833 ,  H01L23/5385 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15787 ,  H05K1/145 ,  H05K3/222 ,  H05K2201/10674 ,  Y10T436/171538 ,  Y10T436/172307 ,  H01L2924/00014 ,  H01L2924/00

摘要： An electronic device and method of packaging an electronic device. The device including: a first substrate, a second substrate and an integrated circuit chip having a first side and an opposite second side, a first set of chip pads on the first side and a second set of chip pads on the second side of the integrated circuit chip, chip pads of the first set of chip pads physically and electrically connected to corresponding substrate pads on the first substrate and chip pads of the second set of chip pads physically and electrically connected to substrate pads of the substrate.

摘要翻译： 一种电子装置和包装电子装置的方法。 该装置包括：第一基板，第二基板和具有第一侧和相对的第二侧的集成电路芯片，在第一侧上的第一组芯片焊盘和在集成的第二侧上的第二组芯片焊盘 电路芯片，第一组芯片焊盘的芯片焊盘物理和电连接到第一衬底上的对应衬底焊盘，并且第二组芯片焊盘的芯片焊盘物理和电连接到衬底的衬底焊盘。

公开(公告)号：US20080042798A1

公开(公告)日：2008-02-21

申请号：US11848263

申请日：2007-08-31

申请人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Terence Hook ,  Robert Rassel ,  Edmund Sprogis ,  Anthony Stamper ,  William Murphy

发明人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Terence Hook ,  Robert Rassel ,  Edmund Sprogis ,  Anthony Stamper ,  William Murphy

IPC分类号： H01C1/08

CPC分类号： H01C7/1013 ,  H01C1/084 ,  H01L2924/0002 ,  Y10T29/49083 ,  Y10T29/49085 ,  Y10T29/49099 ,  Y10T29/49144 ,  Y10T29/49147 ,  H01L2924/00

摘要： A resistor with heat sink is provided. The heat sink includes a conductive path having metal or other thermal conductor having a high thermal conductivity. To avoid shorting the electrical resistor to ground with the thermal conductor, a thin layer of high thermal conductivity electrical insulator is interposed between the thermal conductor and the body of the resistor. Accordingly, a resistor can carry large amounts of current because the high conductivity thermal conductor will conduct heat away from the resistor to a heat sink. Various configurations of thermal conductors and heat sinks are provided offering good thermal conductive properties in addition to reduced parasitic capacitances and other parasitic electrical effects, which would reduce the high frequency response of the electrical resistor.

公开(公告)号：US20070138657A1

公开(公告)日：2007-06-21

申请号：US11314272

申请日：2005-12-21

申请人： Vincenzo Condorelli ,  Claudius Feger ,  Kevin Gotze ,  Nihad Hadzic ,  John Knickerbocker ,  Edmund Sprogis

发明人： Vincenzo Condorelli ,  Claudius Feger ,  Kevin Gotze ,  Nihad Hadzic ,  John Knickerbocker ,  Edmund Sprogis

IPC分类号： H01L23/28

CPC分类号： H01L23/576 ,  H01L23/5383 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/19103 ,  H01L2924/19107 ,  Y10T29/53039 ,  Y10T29/53052 ,  Y10T29/53178 ,  H01L2924/00

摘要： A physically secure processing assembly is provided that includes dies mounted on a substrate so as to sandwich the electrical contacts of the dies between the dies and the substrate. The substrate is provided with substrate contacts and conductive pathways that are electrically coupled to the die contacts and extend through the substrate. Electrical conductors surround the conductive pathways. A monitoring circuit detects a break in continuity of one or more of the electrical conductors, and preferably renders the assembly inoperable. Preferably, an epoxy encapsulation is provided to prevent probing tools from being able to reach the die or substrate contacts.

摘要翻译： 提供了一种物理上安全的处理组件，其包括安装在基板上的模具，以便将模具的电触点夹在模具和基板之间。 衬底设置有电连接到管芯触点并延伸穿过衬底的衬底触点和导电路径。 电导体围绕导电路径。 监控电路检测一个或多个电导体的连续性的断裂，并且优选地使组件不可操作。 优选地，提供环氧树脂封装以防止探测工具能够到达管芯或衬底接触。

公开(公告)号：US20050121768A1

公开(公告)日：2005-06-09

申请号：US10729254

申请日：2003-12-05

申请人： Daniel Edelstein ,  Paul Andry ,  Leena Buchwalter ,  Jon Casey ,  Sherif Goma ,  Raymond Horton ,  Gareth Hougham ,  Michael Lane ,  Xiao Liu ,  Chirag Patel ,  Edmund Sprogis ,  Michelle Steen ,  Brian Sundlof ,  Cornelia Tsang ,  George Walker

发明人： Daniel Edelstein ,  Paul Andry ,  Leena Buchwalter ,  Jon Casey ,  Sherif Goma ,  Raymond Horton ,  Gareth Hougham ,  Michael Lane ,  Xiao Liu ,  Chirag Patel ,  Edmund Sprogis ,  Michelle Steen ,  Brian Sundlof ,  Cornelia Tsang ,  George Walker

IPC分类号： H01L21/48 ,  H01L21/768 ,  H01L23/498 ,  H01L23/48 ,  H01L21/4763

CPC分类号： H01L23/49883 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00

摘要： A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.

摘要翻译： 一种载体结构和方法，用于制造具有通孔的载流子结构，每个导通孔具有导电结构，其有效热膨胀系数小于或接近于基板的热膨胀系数，并且具有小于或等于 或者与衬底的密切匹配。 导电结构可以包括同心的通孔填充区域，其具有同心设置的不同材料，由导电材料的环形环包围的衬底材料的芯，由导电材料的环形环包围的CTE匹配的非导电材料的芯， 具有低CTE的内部空隙的导电通孔，或已经烧结或熔合的诸如金属 - 陶瓷浆料的导电复合材料的完整填充物。

公开(公告)号：US08084858B2

公开(公告)日：2011-12-27

申请号：US12424001

申请日：2009-04-15

申请人： Timothy H. Daubenspeck ,  Wolfgang Sauter ,  Timothy D. Sullivan ,  Steven L. Wright ,  Edmund Sprogis

发明人： Timothy H. Daubenspeck ,  Wolfgang Sauter ,  Timothy D. Sullivan ,  Steven L. Wright ,  Edmund Sprogis

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/03 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/036 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05022 ,  H01L2224/05094 ,  H01L2224/05095 ,  H01L2224/05098 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/11334 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01059 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/05552

摘要： In one embodiment, a sub-pad assembly of metal structures is located directly underneath a metal pad. The sub-pad assembly includes an upper level metal line structure abutting the metal pad, a lower level metal line structure located underneath the upper level metal line structure, and a set of metal vias that provide electrical connection between the lower level metal line structure located underneath the upper level metal line structure. In another embodiment, the reliability of a C4 ball is enhanced by employing a metal pad structure having a set of integrated metal vias that are segmented and distributed to facilitate uniform current density distribution within the C4 ball. The areal density of the cross-sectional area in the plurality of metal vias is higher at the center portion of the metal pad than at the peripheral portion of the planar portion of the metal pad.

摘要翻译： 在一个实施例中，金属结构的子垫组件位于金属垫的正下方。 子焊盘组件包括邻接金属焊盘的上层金属线结构，位于上层金属线结构下方的下层金属线结构，以及一组在下层金属线结构之间提供电连接的金属通孔 在上层金属线结构下方。 在另一个实施例中，C4球的可靠性通过使用具有一组集成金属通孔的金属焊盘结构而被增强，所述集成金属通孔被分段和分配以便于在C4球内均匀的电流密度分布。 在金属焊盘的中心部分，多个金属通孔中的横截面面积的面密度高于在金属焊盘的平面部分的周边部分。

公开(公告)号：US20080067628A1

公开(公告)日：2008-03-20

申请号：US11930698

申请日：2007-10-31

申请人： Raymond Horton ,  John Knickerbocker ,  Edmund Sprogis ,  Cornelia Tsang

发明人： Raymond Horton ,  John Knickerbocker ,  Edmund Sprogis ,  Cornelia Tsang

IPC分类号： H01L29/00

CPC分类号： H01L23/49827 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/5382 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/15311

摘要： Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or mote vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device comprising at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein comprises the following step. One or more of the plurality of decoupling capacitors are selectively deactivated

摘要翻译： 提供电子器件制造技术。 一方面，提供一种电子设备。 该电子设备包括具有一个或多个微通孔和集成在其中的多个去耦电容器的至少一个插入器结构，所述至少一个插入器结构被配置为允许选择性地去激活多个去耦电容器中的一个或多个。 在另一方面，一种制造电子器件的方法，包括至少一个具有一个或多个通孔的内插器结构和集成在其中的多个去耦电容器，其包括以下步骤。 选择性地去激活多个去耦电容器中的一个或多个