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40 条记录 (耗时 0.025 秒)

    Point of use slurry dispensing system
    1.
    发明授权
    Point of use slurry dispensing system 失效
    使用点浆料分配系统

    公开(公告)号：US5478435A

    公开(公告)日：1995-12-26

    申请号：US356987

    申请日：1994-12-16

    申请人： James J. Murphy ,  Janos Farkas ,  Lucia C. Markert ,  Rahul Jairath

    发明人： James J. Murphy ,  Janos Farkas ,  Lucia C. Markert ,  Rahul Jairath

    IPC分类号： B01F3/12 ,  B01F5/04 ,  H01L21/00

    CPC分类号： H01L21/6715 ,  B01F5/0403 ,  B01F2003/1257 ,  B01F2215/0045

    摘要： A point of use slurry dispensing system with controls for dilution, temperature and oxidizer/etchant/additive infusion. A slurry in unmixed form and a diluting agent are independently pumped to a pad on a CMP tool. Liquid heaters are used to heat the slurry and the diluting agent to a desirable temperature. The actual mixing occurs at the point of use on the pad or in a dispensing line just prior to the point of use. In some instances a third independent distribution line is used to dispense an oxidizer, etchant and/or chemical additive at or near the point of use.

    摘要翻译： 一种使用的浆料分配系统，其具有用于稀释，温度和氧化剂/蚀刻剂/添加剂输注的对照。 将未混合的浆料和稀释剂独立地泵送到CMP工具上的垫上。 液体加热器用于将浆料和稀释剂加热至所需温度。 在使用点之前，实际的混合发生在垫上或使用点处。 在一些情况下，使用第三独立分配线来在使用点处或附近分配氧化剂，蚀刻剂和/或化学添加剂。

    Method and structure for dividing a substrate into individual devices
    6.
    发明授权
    Method and structure for dividing a substrate into individual devices 有权
    将基板分割为各个装置的方法和结构

    公开(公告)号：US08343852B2

    公开(公告)日：2013-01-01

    申请号：US13095584

    申请日：2011-04-27

    申请人： Minhua Li ,  Qi Wang ,  Gordon Sim ,  Matthew Reynolds ,  Suku Kim ,  James J. Murphy ,  Hamza Yilmaz

    发明人： Minhua Li ,  Qi Wang ,  Gordon Sim ,  Matthew Reynolds ,  Suku Kim ,  James J. Murphy ,  Hamza Yilmaz

    IPC分类号： H01L21/00

    CPC分类号： H01L21/78

    摘要： A method for obtaining individual dies from a semiconductor structure is disclosed. The semiconductor structure includes a device layer, and the device layer in turn includes active regions separated by predefined spacings. Thick metal is selectively formed on backside of the device layer such that thick metal is formed on backside of active regions but not on backside of the predefined spacings. The semiconductor structure is then cut along the predefined spacings to separate the active regions with thick metal on their backside into individual dies.

    摘要翻译： 公开了一种从半导体结构获得单个管芯的方法。 半导体结构包括器件层，器件层又包括由预定间隔隔开的有源区。 在器件层的背侧选择性地形成厚金属，使得在有源区的背面形成厚金属，而不在预定间隔的背面形成厚金属。 然后沿着预定的间隔切割半导体结构，以将其背面的厚金属的活性区域分离成单独的管芯。

    Semiconductor devices and methods for making the same
    8.
    发明授权
    Semiconductor devices and methods for making the same 有权
    半导体器件及其制造方法

    公开(公告)号：US08129778B2

    公开(公告)日：2012-03-06

    申请号：US12629232

    申请日：2009-12-02

    申请人： Suku Kim ,  James J. Murphy ,  Gary Dolny

    发明人： Suku Kim ,  James J. Murphy ,  Gary Dolny

    IPC分类号： H01L21/00

    CPC分类号： H01L29/8083 ,  H01L29/0634 ,  H01L29/1066 ,  H01L29/7722

    摘要： Semiconductor devices and methods for making such devices that are especially suited for high-frequency applications are described. The semiconductor devices combine a SIT (or a junction field-effect transistor [JFET]) architecture with a PN super-junction structure. The SIT architecture can be made using a trench formation containing a gate that is sandwiched between thick dielectric layers. While the gate is vertically sandwiched between the two isolating regions in the trench, it is also connected to a region of one conductivity type of the super-junction structure, thereby allowing control of the current path of the semiconductor device. Such semiconductor devices have a lower specific resistance and capacitance relative to conventional planar gate and recessed gate SIT semiconductor devices. Other embodiments are described.

    摘要翻译： 描述了用于制造这种特别适用于高频应用的器件的半导体器件和方法。 半导体器件将SIT（或结型场效应晶体管[JFET]）结构与PN超结结构相结合。 SIT结构可以使用包含夹在厚介电层之间的栅极的沟槽形成。 当栅极垂直夹在沟槽中的两个隔离区域之间时，其也连接到一个导电类型的超结结构的区域，从而允许控制半导体器件的电流路径。 这种半导体器件相对于传统的平面栅极和凹入栅极SIT半导体器件具有较低的电阻率和电容。 描述其他实施例。

    High aspect ratio trench structures with void-free fill material
    10.
    发明授权
    High aspect ratio trench structures with void-free fill material 有权
    具有无孔填充材料的高纵横比沟槽结构

    公开(公告)号：US07956411B2

    公开(公告)日：2011-06-07

    申请号：US12353909

    申请日：2009-01-14

    申请人： James J. Murphy ,  Hui Chen ,  Eileen Valdez

    发明人： James J. Murphy ,  Hui Chen ,  Eileen Valdez

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/495 ,  H01L29/4975 ,  H01L29/66727 ,  H01L29/66734

    摘要： A field effect transistor (FET) includes a trench extending into a semiconductor region. A conductive electrode is disposed in the trench, and the conductive electrode is insulated from the semiconductor region by a dielectric layer. The conductive electrode includes a conductive liner lining the dielectric layer along opposite sidewalls of the trench. The conductive liner has tapered edges such that a thickness of the conductive liner gradually increases from a top surface of the conductive electrode to a point in lower half of the conductive electrode. The conductive electrode further includes a conductive fill material sandwiched by the conductive liner. The FET further includes a drift region of a first conductivity type in the semiconductor region, and a body region of a second conductivity type extending over the drift region. Source regions of the first conductivity type extend in the body region adjacent the trench.

    摘要翻译： 场效应晶体管（FET）包括延伸到半导体区域中的沟槽。 导电电极设置在沟槽中，导电电极通过电介质层与半导体区域绝缘​​。 导电电极包括沿着沟槽的相对侧壁衬在电介质层上的导电衬垫。 导电衬垫具有锥形边缘，使得导电衬垫的厚度从导电电极的顶表面逐渐增加到导电电极的下半部分。 导电电极还包括被导电衬垫夹住的导电填充材料。 FET还包括半导体区域中的第一导电类型的漂移区域和在漂移区域上延伸的第二导电类型的体区域。 第一导电类型的源区在与沟槽相邻的体区中延伸。