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    Single step, high temperature nucleation process for a lattice mismatched substrate
    1.
    发明授权
    Single step, high temperature nucleation process for a lattice mismatched substrate 有权
    单步，高温成核过程的晶格失配衬底

    公开(公告)号：US07250360B2

    公开(公告)日：2007-07-31

    申请号：US11069040

    申请日：2005-03-02

    申请人： James R. Shealy ,  Joseph A. Smart

    发明人： James R. Shealy ,  Joseph A. Smart

    IPC分类号： H01L21/28 ,  H01L21/3205

    CPC分类号： H01L21/02562 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/02557 ,  H01L21/0262 ,  H01L21/02658

    摘要： A single step process for nucleation and subsequent epitaxial growth on a lattice mismatched substrate is achieved by pre-treating the substrate surface with at least one group III reactant or at least one group II reactant prior to the introduction of a group V reactant or a group VI reactant. The group III reactant or the group II reactant is introduced into a growth chamber at an elevated growth temperature to wet a substrate surface prior to any actual crystal growth. Once the pre-treatment of the surface is complete, a group V reactant or a group VI reactant is introduced to the growth chamber to commence the deposition of a nucleation layer. A buffer layer is then grown on the nucleation layer providing a surface upon which the epitaxial layer is grown preferably without changing the temperature within the chamber.

    摘要翻译： 通过在引入V族反应物或基团之前用至少一种III族反应物或至少一种II族反应物预处理底物表面来实现晶格失配衬底上的成核和随后的外延生长的单步过程 VI反应物。 将III族反应物或II族反应物在升高的生长温度下引入生长室中，以在任何实际的晶体生长之前润湿基底表面。 一旦表面的预处理完成，将V族反应物或VI族反应物引入生长室，开始沉积成核层。 然后在成核层上生长缓冲层，提供外延层生长的表面，而不改变室内的温度。

    Single step process for epitaxial lateral overgrowth of nitride based materials
    2.
    发明授权
    Single step process for epitaxial lateral overgrowth of nitride based materials 失效
    用于氮化物基材料外延横向过度生长的单步法

    公开(公告)号：US06478871B1

    公开(公告)日：2002-11-12

    申请号：US09676938

    申请日：2000-10-02

    申请人： James R. Shealy ,  Joseph A. Smart

    发明人： James R. Shealy ,  Joseph A. Smart

    IPC分类号： C30B2504

    CPC分类号： C30B25/02 ,  C30B29/403 ,  C30B29/406 ,  H01L21/02378 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02647

    摘要： An epitaxial deposition process produces epitaxial lateral overgrowth (ELO) of nitride based materials directly a patterned substrate (10). The substrate (10) is preferably formed from SiC or sapphire, and is patterned with a mask (12), preferably formed of silicon nitride, having a plurality of openings (13) formed therein. A nucleation layer (14), preferably formed of AlGaN, is grown at a high reactor temperature of 700-1100 degrees C., which wets the exposed substrate surface, without significant nucleation on the mask (12). This eliminates the need for regrowth while producing smooth growth surfaces in the window openings (13) as well as over the mask (12). Subsequent deposition of a nitride based material layer (16), preferably GaN, results in a relatively defect free planar surfaced material grown laterally over the mask (12).

    摘要翻译： 外延沉积工艺直接对图案化的衬底（10）产生氮化物基材料的外延横向过度生长（ELO）。 衬底（10）优选地由SiC或蓝宝石形成，并且用在其中形成有多个开口（13）的掩模（12）图案化，优选由氮化硅形成。 优选由AlGaN形成的成核层（14）在700-1100℃的高反应器温度下生长，其在暴露的基底表面上润湿，而在掩模（12）上没有显着的成核。 这消除了在窗口（13）中以及面罩（12）上方产生光滑生长表面的同时需要再生长。 随后沉积氮化物基材料层（16），优选GaN，导致在掩模（12）上横向生长的相对缺陷的平坦表面材料。

    Gated III-V semiconductor structure and method
    3.
    发明授权
    Gated III-V semiconductor structure and method 有权
    门III-V半导体结构及方法

    公开(公告)号：US09299821B2

    公开(公告)日：2016-03-29

    申请号：US13389127

    申请日：2011-06-22

    申请人： James R. Shealy ,  Richard Brown

    发明人： James R. Shealy ,  Richard Brown

    IPC分类号： H01L21/02 ,  H01L29/778 ,  H01L23/29 ,  H01L29/66 ,  H01L23/31 ,  H01L29/10 ,  H01L29/20

    CPC分类号： H01L29/778 ,  H01L21/02381 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7786 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A gated III-V semiconductor structure and a method for fabricating the gated III-V semiconductor structure includes a threshold modifying dopant region within a III-V semiconductor barrier layer at the base of an aperture through a passivation layer that otherwise passivates the III-V semiconductor barrier layer. The passivation layer, which may comprise an aluminum-silicon nitride material, has particular bandgap and permittivity properties that provide for enhanced performance of a III-V semiconductor device that derives from the III-V semiconductor structure absent a field plate. The threshold modifying dopant region provides the possibility for forming both an enhancement mode gated III-V semiconductor structure and a depletion mode III-V semiconductor structure on the same substrate. The threshold modifying dopant region when comprising a magnesium (Mg) threshold modifying dopant may be incorporated into the gates III-V semiconductor structure using a dicyclopentadienyl magnesium (Cp2Mg) vapor diffusion method or a magnesium-silicon nitride (MgSiN) solid state diffusion method.

    摘要翻译： 门III-V半导体结构和用于制造栅极III-V半导体结构的方法包括在通过钝化层的孔底部的III-V半导体阻挡层内的阈值修改掺杂剂区域，否则钝化层III-V 半导体阻挡层。 可以包括铝 - 氮化硅材料的钝化层具有特定的带隙和介电常数特性，其提供了不存在场板的III-V半导体结构的III-V半导体器件的增强的性能。 阈值修改掺杂剂区域提供在同一衬底上形成增强模式门控III-V半导体结构和耗尽型III-V半导体结构的可能性。 使用二环戊二烯基镁（Cp2Mg）蒸气扩散法或镁 - 氮化硅（MgSiN）固态扩散法可以将包含镁（Mg）阈值修饰掺杂剂的阈值修饰掺杂剂区域结合到栅极III-V半导体结构中。

    Process for synthesis of cubic GaN on GaAs using NH.sub.3 in an RF plasma process
    5.
    发明授权
    Process for synthesis of cubic GaN on GaAs using NH.sub.3 in an RF plasma process 失效
    在RF等离子体工艺中使用NH 3在GaAs上合成立方氮化镓的工艺

    公开(公告)号：US5834379A

    公开(公告)日：1998-11-10

    申请号：US680874

    申请日：1996-07-16

    申请人： James R. Shealy ,  James R. Engstrom ,  Yu-Hwa Lo

    发明人： James R. Shealy ,  James R. Engstrom ,  Yu-Hwa Lo

    IPC分类号： C23C8/36 ,  C23C11/08

    CPC分类号： C23C8/36

    摘要： A process for synthesizing wide band gap materials, specifically, GaN, employs plasma-assisted and thermal nitridation with NH.sub.3 to convert GaAs to GaN. Thermal assisted nitridation with NH.sub.3 can be employed for forming layers of substantial thickness (on the order of 1 micron) of cubic and hexagonal GaN on a GaAs substrate. Plasma-assisted nitridation of NH.sub.3 results in formation of predominantly cubic GaN, a form particularly useful in optoelectronic devices. Preferably, very thin GaAs membranes are employed to permit formation thereon of GaN layers of any desired thickness without concern for critical thickness constraints. The thin membranes are preferably formed either with an epitaxial bonding technique, or by undercut etching.

    摘要翻译： 用于合成宽带隙材料，特别是GaN的方法采用NH 3等离子体辅助和热氮化将GaAs转化为GaN。 使用NH 3的热辅助氮化可用于在GaAs衬底上形成基本上厚度（约1微米）的立方体和六边形GaN的层。 NH 3的等离子体辅助氮化导致主要形成立方GaN，这是在光电器件中特别有用的形式。 优选地，使用非常薄的GaAs膜以允许在其上形成任何所需厚度的GaN层，而不考虑临界厚度限制。 薄膜优选地通过外延键合技术或通过底切蚀刻来形成。

    High power (1,4 W)AlGaInP graded-index separate confinement heterostructure visible (.lambda.-658 nm) laser
    6.
    发明授权
    High power (1,4 W)AlGaInP graded-index separate confinement heterostructure visible (.lambda.-658 nm) laser 失效
    大功率（1,4W）AlGaInP渐变折射率分离的限制异质结构可见（λ-658nm）激光

    公开(公告)号：US5003548A

    公开(公告)日：1991-03-26

    申请号：US247206

    申请日：1988-09-21

    申请人： David P. Bour ,  James R. Shealy

    发明人： David P. Bour ,  James R. Shealy

    IPC分类号： H01S5/34 ,  H01S5/343

    CPC分类号： B82Y20/00 ,  H01S5/34326 ,  H01S5/3409

    摘要： Single quantum well short wavelength AlGaInP GRIN-SCH semiconductor lasers having high output power in the 660-680 nm range were prepared by organometallic vapor phase epitaxy. The laser active region preferably consists of a 100 .ANG. single Ga.sub.0.5 In.sub.0.5 P quantum well and 1600 .ANG. graded index regions on both sides of the well. The graded index regions were produced by lattice-matched graded composition (Al.sub.y Ga.sub.1-y).sub.0.5 In.sub.0.5 P quaternary alloys where y has a value from about 0.2 to 0.6. This structure reduces the broad-area threshold current compared to a double heterostructure laser to give pulsed thresholds as low as 1050 A/cm.sup.2. Total pulsed power of 1.4 W at 658 nm is available from an 80 .mu.m.times.300 .mu.m mesa-stripe laser. A differential quantum efficiency of up to about .about.56% was measured. Indicated uses include diode-pumped solid state laser applications and as a light source in optical disk drives and holographic scanners.

    摘要翻译： 通过有机金属气相外延制备在660-680nm范围内具有高输出功率的单量子阱短波长AlGaInP GRIN-SCH半导体激光器。 激光有源区优选由井的两侧上的100个ANGSTROM单个Ga0.5In0.5P量子阱和1600个ANGSTROM分级索引区组成。 渐变折射率区域由晶格匹配的梯度组成（AlyGa1-y）0.5In0.5P四元合金制成，其中y具有约0.2至0.6的值。 与双异质结构激光器相比，该结构减小了宽区域阈值电流，以提供低至1050A / cm 2的脉冲阈值。 在658nm处的总脉冲功率为1.4W，可从80μm×300μm的台面条纹激光器获得。 测量高达约差异量子效率的差分量子效率为56％。 指示用途包括二极管泵浦固态激光器应用以及作为光盘驱动器和全息扫描器中的光源。

    Chemical vapor deposition process for aluminum silicon nitride
    8.
    发明授权
    Chemical vapor deposition process for aluminum silicon nitride 有权
    氮化硅铝化学气相沉积工艺

    公开(公告)号：US08791034B2

    公开(公告)日：2014-07-29

    申请号：US13380144

    申请日：2010-06-28

    申请人： James R. Shealy ,  Richard Brown

    发明人： James R. Shealy ,  Richard Brown

    IPC分类号： H01L21/318 ,  H01L21/443

    CPC分类号： H01L21/318 ,  C23C16/34 ,  H01L21/02145 ,  H01L21/02271

    摘要： A chemical vapor deposition method for forming an aluminum-silicon nitride layer upon a substrate uses an aluminum precursor, a silicon precursor and a nitrogen precursor under chemical vapor deposition conditions to deposit the aluminum-silicon nitride layer upon the substrate. The aluminum-silicon nitride layer has an index of refraction interposed between silicon nitride and aluminum nitride. The aluminum-silicon nitride layer also has a bandgap from about 4.5 to about 6 eV and a permittivity from about 6×10^-11 to about 8×10^-11 F/m. The aluminum-silicon nitride layer may be further thermally annealed to reduce a hydrogen content of the aluminum-silicon nitride layer.

    摘要翻译： 用于在基板上形成铝 - 氮化硅层的化学气相沉积方法在化学气相沉积条件下使用铝前体，硅前驱体和氮前体，以将铝 - 氮化硅层沉积在基底上。 铝硅氮化物层具有置于氮化硅和氮化铝之间的折射率。 铝 - 氮化硅层还具有约4.5至约6eV的带隙，介电常数约为6×10 ^ -11至约8×10 ^ -11F / m。 铝 - 氮化硅层可进一步热退火以降低铝 - 氮化硅层的氢含量。

    Vertical channel field effect transistor
    10.
    发明授权
    Vertical channel field effect transistor 失效
    垂直沟道场效应晶体管

    公开(公告)号：US4343015A

    公开(公告)日：1982-08-03

    申请号：US149936

    申请日：1980-05-14

    申请人： Bantval J. Baliga ,  James R. Shealy

    发明人： Bantval J. Baliga ,  James R. Shealy

    IPC分类号： H01L21/338 ,  H01L29/10 ,  H01L29/423 ,  H01L29/812

    CPC分类号： H01L29/66856 ,  H01L29/1025 ,  H01L29/42316 ,  H01L29/8122

    摘要： Improved high frequency GaAs FETs have a higher breakdown voltage, lower input gate capacitance and lower source (or drain) resistance. A preferentially etched groove structure yields parallel trapezoidal semiconductor fingers that are wider at the top than at the bottom. Every finger intersects a high resistivity, semi-insulating region which surrounds the active device area and is fabricated by high energy particle bombardment. Metal gates are deposited within the grooves on three sides of the trapezoidal fingers.

    摘要翻译： 改进的高频GaAs FET具有更高的击穿电压，较低的输入栅极电容和较低的源极（或漏极）电阻。 优先蚀刻的凹槽结构产生在顶部比底部更宽的平行梯形半导体指状物。 每个指状物与围绕有源器件区域的高电阻率半绝缘区域相交，并且通过高能量粒子轰击制造。 金属门沉积在梯形手指三侧的槽内。