公开(公告)号：US09099347B2

公开(公告)日：2015-08-04

申请号：US13415388

申请日：2012-03-08

申请人： Jang-Gn Yun ,  Kwang Soo Seol ,  Youngwoo Park

发明人： Jang-Gn Yun ,  Kwang Soo Seol ,  Youngwoo Park

IPC分类号： H01L29/76 ,  H01L27/115

CPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

摘要： Provided are three-dimensional semiconductor memory devices and methods of fabricating the same. The device may include an electrode structure extending in a first direction and including electrodes and insulating patterns which are alternately and repeatedly stacked on a substrate, and vertical active patterns penetrating the electrode structure. At least an uppermost electrode of the electrodes is divided into a plurality of physically isolated segments arranged in the first direction. The segments of the uppermost electrode are electrically connected to each other.

摘要翻译： 提供三维半导体存储器件及其制造方法。 该器件可以包括在第一方向上延伸的电极结构，并且包括电极和交替重复堆叠在基板上的绝缘图案，以及穿透电极结构的垂直有源图案。 至少电极的最上面的电极被分成沿着第一方向布置的多个物理隔离的部分。 最上面的电极的电极彼此电连接。

公开(公告)号：US20120280299A1

公开(公告)日：2012-11-08

申请号：US13415388

申请日：2012-03-08

申请人： Jang-Gn Yun ,  Kwang Soo Seol ,  Youngwoo Park

发明人： Jang-Gn Yun ,  Kwang Soo Seol ,  Youngwoo Park

IPC分类号： H01L29/68

CPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

摘要： Provided are three-dimensional semiconductor memory devices and methods of fabricating the same. The device may include an electrode structure extending in a first direction and including electrodes and insulating patterns which are alternately and repeatedly stacked on a substrate, and vertical active patterns penetrating the electrode structure. At least an uppermost electrode of the electrodes is divided into a plurality of physically isolated segments arranged in the first direction. The segments of the uppermost electrode are electrically connected to each other.

摘要翻译： 提供三维半导体存储器件及其制造方法。 该器件可以包括在第一方向上延伸的电极结构，并且包括电极和交替重复堆叠在基板上的绝缘图案，以及穿透电极结构的垂直有源图案。 至少电极的最上面的电极被分成沿着第一方向布置的多个物理隔离的部分。 最上面的电极的电极彼此电连接。

公开(公告)号：US08674429B2

公开(公告)日：2014-03-18

申请号：US13759195

申请日：2013-02-05

申请人： Jang-Gn Yun ,  Jung-Dal Choi ,  Kwang-Soo Seol

发明人： Jang-Gn Yun ,  Jung-Dal Choi ,  Kwang-Soo Seol

IPC分类号： H01L21/02

CPC分类号： H01L29/7926 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/792

摘要： A gate structure of a non-volatile memory device and a method of forming the same including a tunnel oxide layer pattern, a charge trap layer pattern, a blocking dielectric layer pattern having the uppermost layer including a material having a first dielectric constant greater than that of a material included in the tunnel oxide layer pattern, and first and second conductive layer patterns. The gate structure includes a first spacer to cover at least the sidewall of the second conductive layer pattern. The gate structure includes a second spacer covering the sidewall of the first spacer and the sidewall of the first conductive layer pattern and including a material having a second dielectric constant equal to or greater than the first dielectric constant. In the non-volatile memory device including the gate structure, erase saturation caused by back tunneling is reduced.

公开(公告)号：US08587052B2

公开(公告)日：2013-11-19

申请号：US13402171

申请日：2012-02-22

申请人： Jang-Gn Yun ,  Kwang-Soo Seol ,  Jungdal Choi

发明人： Jang-Gn Yun ,  Kwang-Soo Seol ,  Jungdal Choi

IPC分类号： H01L29/792

CPC分类号： H01L29/7926 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66833

摘要： One example embodiment of a semiconductor device includes a memory cell array formed on a substrate. The memory cell array includes a gate stack including alternating conductive and insulating layers. A first lower conductive layer in the gate stack has a portion disposed below a first upper conductive layer in the gate stack, and a first contact area of the first lower conductive layer is disposed higher than a second contact area of the first upper conductive layer. The semiconductor device further includes first and second contact plugs extending into the gate stack to contact the first and second contact areas, respectively.

摘要翻译： 半导体器件的一个示例实施例包括形成在衬底上的存储单元阵列。 存储单元阵列包括包括交替的导电和绝缘层的栅极堆叠。 栅堆叠中的第一下导电层具有设置在栅极堆叠中的第一上导电层下方的部分，并且第一下导电层的第一接触区域设置为高于第一上导电层的第二接触面积。 半导体器件还包括分别延伸到栅极堆叠中以分别接触第一和第二接触区域的第一和第二接触插塞。

公开(公告)号：US20130032875A1

公开(公告)日：2013-02-07

申请号：US13402171

申请日：2012-02-22

申请人： Jang-Gn Yun ,  Kwang-Soo Seol ,  Jungdal Choi

发明人： Jang-Gn Yun ,  Kwang-Soo Seol ,  Jungdal Choi

IPC分类号： H01L29/792 ,  H01L29/78

CPC分类号： H01L29/7926 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66833

摘要： One example embodiment of a semiconductor device includes a memory cell array formed on a substrate. The memory cell array includes a gate stack including alternating conductive and insulating layers. A first lower conductive layer in the gate stack has a portion disposed below a first upper conductive layer in the gate stack, and a first contact area of the first lower conductive layer is disposed higher than a second contact area of the first upper conductive layer. The semiconductor device further includes first and second contact plugs extending into the gate stack to contact the first and second contact areas, respectively.

摘要翻译： 半导体器件的一个示例实施例包括形成在衬底上的存储单元阵列。 存储单元阵列包括包括交替的导电和绝缘层的栅极堆叠。 栅堆叠中的第一下导电层具有设置在栅极堆叠中的第一上导电层下方的部分，并且第一下导电层的第一接触区域设置为高于第一上导电层的第二接触面积。 半导体器件还包括分别延伸到栅极堆叠中以分别接触第一和第二接触区域的第一和第二接触插塞。

公开(公告)号：US09741733B2

公开(公告)日：2017-08-22

申请号：US14962263

申请日：2015-12-08

申请人： Joon-Sung Lim ,  Jang-Gn Yun ,  Jaesun Yun

发明人： Joon-Sung Lim ,  Jang-Gn Yun ,  Jaesun Yun

IPC分类号： H01L27/115 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11573

CPC分类号： H01L27/11582 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11573 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices and methods of manufacturing the semiconductor devices are provided. The semiconductor devices may include a semiconductor pattern including an opening on a semiconductor substrate. A peripheral transistor and a peripheral interconnection structure may be disposed between the semiconductor substrate and the semiconductor pattern. The peripheral interconnection structure may be electrically connected to the peripheral transistor. Cell gate conductive patterns may be disposed on the semiconductor pattern. The cell vertical structures may extend through the cell gate conductive patterns and may be connected to the semiconductor pattern. Cell bit line contact plugs may be disposed on the cell vertical structures. A bit line may be disposed on the cell bit line contact plugs. A peripheral bit line contact structure may be disposed between the bit line and the peripheral interconnection structure. The peripheral bit line contact structure may extend through the opening of the semiconductor.

公开(公告)号：US20170069636A1

公开(公告)日：2017-03-09

申请号：US15160335

申请日：2016-05-20

申请人： Se-Jun PARK ,  Jang-Gn Yun ,  Sung-Min Hwang ,  Ahn-Sik Moon ,  Zhiliang Xia

发明人： Se-Jun PARK ,  Jang-Gn Yun ,  Sung-Min Hwang ,  Ahn-Sik Moon ,  Zhiliang Xia

IPC分类号： H01L27/115 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L27/1157 ,  H01L27/11582

摘要： A semiconductor device includes a plurality of insulation patterns and a plurality of gates alternately and repeatedly stacked on a substrate, a channel pattern extending through the gates in a first direction substantially perpendicular to a top surface of the substrate, a semiconductor pattern between the channel pattern and the substrate, and a conductive pattern between the channel pattern and the semiconductor pattern. The conductive pattern electrically connects the channel pattern to the semiconductor pattern. The conductive pattern contacts a bottom edge of the channel pattern and an upper surface of the semiconductor pattern.

摘要翻译： 一种半导体器件包括多个绝缘图案和多个栅极交替重复堆叠在基板上，沟道图案沿基本上垂直于基板顶表面的第一方向延伸穿过栅极，沟道图案 和衬底，以及沟道图案和半导体图案之间的导电图案。 导电图案将沟道图案电连接到半导体图案。 导电图案接触通道图案的底部边缘和半导体图案的上表面。

公开(公告)号：US09728549B2

公开(公告)日：2017-08-08

申请号：US14974567

申请日：2015-12-18

申请人： Jang-Gn Yun ,  Sunghoi Hur ,  Jaesun Yun ,  Joon-Sung Lim

发明人： Jang-Gn Yun ,  Sunghoi Hur ,  Jaesun Yun ,  Joon-Sung Lim

IPC分类号： H01L27/11582 ,  H01L27/11573 ,  H01L27/11575

CPC分类号： H01L27/11582 ,  H01L27/11573 ,  H01L27/11575

摘要： A semiconductor device may include a cell gate conductive pattern in a cell array area that extends to a step area, a cell vertical structure in the cell array area that extends through the cell gate conductive pattern, a cell gate contact structure on the cell gate conductive pattern in the step area, a cell gate contact region in the cell gate conductive pattern and aligned with the cell gate contact structure, a first peripheral contact structure spaced apart from the cell gate conductive pattern, a second peripheral contact structure spaced apart from the first peripheral contact structure, a first peripheral contact region under the first peripheral contact structure, and a second peripheral contact region under the second peripheral contact structure. The cell gate contact region may include a first element and a remainder of the cell gate conductive pattern may not substantially include the first element.

公开(公告)号：US09184174B2

公开(公告)日：2015-11-10

申请号：US14155649

申请日：2014-01-15

申请人： Jang-Gn Yun ,  Hongsoo Kim ,  Aaron Park ,  Hoosung Cho

发明人： Jang-Gn Yun ,  Hongsoo Kim ,  Aaron Park ,  Hoosung Cho

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L27/115

CPC分类号： H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices are provided. A semiconductor device may include a substrate and a plurality of lines on the substrate. The semiconductor device may include a dielectric layer on the substrate and adjacent the plurality of lines. The semiconductor device may include a connection element in the dielectric layer. In some embodiments, the semiconductor device may include a plurality of contacts on the connection element, and a conductive interconnection on one of the plurality of contacts that are on the connection element and on a contact that is spaced apart from the connection element.

摘要翻译： 提供半导体器件。 半导体器件可以包括衬底和衬底上的多条线。 半导体器件可以包括在衬底上并与多条线相邻的电介质层。 该半导体器件可以包括介电层中的连接元件。 在一些实施例中，半导体器件可以包括连接元件上的多个触点，以及在连接元件上的多个触点中的一个触点上以及与连接元件间隔开的触点上的导电互连。

公开(公告)号：US20150084204A1

公开(公告)日：2015-03-26

申请号：US14313031

申请日：2014-06-24

申请人： Jang-Gn Yun ,  Jaesun Yun ,  Hoosung Cho

发明人： Jang-Gn Yun ,  Jaesun Yun ,  Hoosung Cho

IPC分类号： H01L27/112 ,  H01L21/768 ,  H01L23/48

CPC分类号： H01L21/76895 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76831 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/11534 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are a semiconductor device and a method of fabricating the same. The device may include a substrate including a cell array region and a peripheral circuit region, stacks on the cell array region of the substrate, the stacks having a first height and extending along a direction, a common source structure disposed between adjacent ones of the stacks, a peripheral logic structure disposed on the peripheral circuit region of the substrate and having a second height smaller than the first height, a plurality of upper interconnection lines disposed on the peripheral logic structure and extending parallel to each other, and a interconnection structure disposed between the peripheral logic structure and the upper interconnection lines, when viewed in vertical section, and electrically connected to at least two of the upper interconnection lines.

摘要翻译： 提供半导体器件及其制造方法。 该器件可以包括包括单元阵列区域和外围电路区域的衬底，堆叠在衬底的单元阵列区域上，堆叠具有第一高度并沿着方向延伸，布置在相邻堆叠之间的公共源结构 ，设置在所述基板的外围电路区域上并且具有小于所述第一高度的第二高度的外围逻辑结构，设置在所述外围逻辑结构上并且彼此平行延伸的多个上部互连线，以及布置在 周边逻辑结构和上互连线，当从垂直截面看时，并且电连接到至少两个上互连线。