公开(公告)号：US09099347B2

公开(公告)日：2015-08-04

申请号：US13415388

申请日：2012-03-08

申请人： Jang-Gn Yun ,  Kwang Soo Seol ,  Youngwoo Park

发明人： Jang-Gn Yun ,  Kwang Soo Seol ,  Youngwoo Park

IPC分类号： H01L29/76 ,  H01L27/115

CPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

摘要： Provided are three-dimensional semiconductor memory devices and methods of fabricating the same. The device may include an electrode structure extending in a first direction and including electrodes and insulating patterns which are alternately and repeatedly stacked on a substrate, and vertical active patterns penetrating the electrode structure. At least an uppermost electrode of the electrodes is divided into a plurality of physically isolated segments arranged in the first direction. The segments of the uppermost electrode are electrically connected to each other.

摘要翻译： 提供三维半导体存储器件及其制造方法。 该器件可以包括在第一方向上延伸的电极结构，并且包括电极和交替重复堆叠在基板上的绝缘图案，以及穿透电极结构的垂直有源图案。 至少电极的最上面的电极被分成沿着第一方向布置的多个物理隔离的部分。 最上面的电极的电极彼此电连接。

公开(公告)号：US20120280299A1

公开(公告)日：2012-11-08

申请号：US13415388

申请日：2012-03-08

申请人： Jang-Gn Yun ,  Kwang Soo Seol ,  Youngwoo Park

发明人： Jang-Gn Yun ,  Kwang Soo Seol ,  Youngwoo Park

IPC分类号： H01L29/68

CPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

摘要： Provided are three-dimensional semiconductor memory devices and methods of fabricating the same. The device may include an electrode structure extending in a first direction and including electrodes and insulating patterns which are alternately and repeatedly stacked on a substrate, and vertical active patterns penetrating the electrode structure. At least an uppermost electrode of the electrodes is divided into a plurality of physically isolated segments arranged in the first direction. The segments of the uppermost electrode are electrically connected to each other.

摘要翻译： 提供三维半导体存储器件及其制造方法。 该器件可以包括在第一方向上延伸的电极结构，并且包括电极和交替重复堆叠在基板上的绝缘图案，以及穿透电极结构的垂直有源图案。 至少电极的最上面的电极被分成沿着第一方向布置的多个物理隔离的部分。 最上面的电极的电极彼此电连接。

公开(公告)号：US09111617B2

公开(公告)日：2015-08-18

申请号：US13585963

申请日：2012-08-15

申请人： Sunil Shim ,  Jang-gn Yun ,  Jeonghyuk Choi ,  Kwang Soo Seol ,  Jaehoon Jang ,  Jungdal Choi

发明人： Sunil Shim ,  Jang-gn Yun ,  Jeonghyuk Choi ,  Kwang Soo Seol ,  Jaehoon Jang ,  Jungdal Choi

IPC分类号： H01L29/78 ,  G11C16/04 ,  H01L27/115

CPC分类号： G11C16/0466 ,  G11C16/0483 ,  H01L23/535 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device is provided including first and second cell strings formed on a substrate, the first and second cell strings jointly connected to a bit line, wherein each of the first and second cell strings includes a ground selection unit, a memory cell, and first and second string selection units sequentially formed on the substrate to be connected to each other, wherein the ground selection unit is connected to a ground selection line, the memory cell is connected to a word line, the first string selection unit is connected to a first string selection line, and the second string selection unit is connected to a second string selection line, and wherein the second string selection unit of the first cell string has a channel dopant region.

摘要翻译： 提供一种半导体存储器件，包括形成在衬底上的第一和第二单元串，第一和第二单元串共同连接到位线，其中第一和第二单元串中的每一个包括地选择单元，存储单元和 第一和第二串选择单元，其顺序地形成在要连接的基板上，其中，所述接地选择单元连接到地选择线，所述存储单元连接到字线，所述第一串选择单元连接到 第一串选择线，第二串选择单元连接到第二串选择线，并且其中第一单元串的第二串选择单元具有沟道掺杂区。

公开(公告)号：US20130092994A1

公开(公告)日：2013-04-18

申请号：US13585963

申请日：2012-08-15

申请人： Sunil SHIM ,  Jang-gn Yun ,  Jeonghyuk Choi ,  Kwang Soo Seol ,  Jaehoon Jang ,  Jungdal Choi

发明人： Sunil SHIM ,  Jang-gn Yun ,  Jeonghyuk Choi ,  Kwang Soo Seol ,  Jaehoon Jang ,  Jungdal Choi

IPC分类号： H01L29/78

CPC分类号： G11C16/0466 ,  G11C16/0483 ,  H01L23/535 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device is provided including first and second cell strings formed on a substrate, the first and second cell strings jointly connected to a bit line, wherein each of the first and second cell strings includes a ground selection unit, a memory cell, and first and second string selection units sequentially formed on the substrate to be connected to each other, wherein the ground selection unit is connected to a ground selection line, the memory cell is connected to a word line, the first string selection unit is connected to a first string selection line, and the second string selection unit is connected to a second string selection line, and wherein the second string selection unit of the first cell string has a channel dopant region.

公开(公告)号：US08530959B2

公开(公告)日：2013-09-10

申请号：US13198234

申请日：2011-08-04

申请人： Sung-Il Chang ,  Youngwoo Park ,  Kwang Soo Seol

发明人： Sung-Il Chang ,  Youngwoo Park ,  Kwang Soo Seol

IPC分类号： H01L29/78

CPC分类号： H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

摘要： Provided are three-dimensional semiconductor devices. A device includes an electrode structure including conductive patterns sequentially stacked on a substrate, a semiconductor pattern penetrating the electrode structure and including channel regions adjacent to the conductive patterns and vertical adjacent regions between the channel regions, and a semiconductor connecting layer extending from an outer sidewall of the semiconductor pattern to connect the semiconductor pattern to the substrate.

摘要翻译： 提供三维半导体器件。 一种器件包括：电极结构，包括依次层叠在衬底上的导电图案，穿透电极结构的半导体图案，以及包括与导电图案相邻的沟道区域和沟道区域之间的垂直相邻区域;以及从外侧壁延伸的半导体连接层 的半导体图案以将半导体图案连接到基板。

公开(公告)号：US20120043673A1

公开(公告)日：2012-02-23

申请号：US13198234

申请日：2011-08-04

申请人： SUNG-IL CHANG ,  Youngwoo Park ,  Kwang Soo Seol

发明人： SUNG-IL CHANG ,  Youngwoo Park ,  Kwang Soo Seol

IPC分类号： H01L23/52

CPC分类号： H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

摘要： Provided are three-dimensional semiconductor devices. A device includes an electrode structure including conductive patterns sequentially stacked on a substrate, a semiconductor pattern penetrating the electrode structure and including channel regions adjacent to the conductive patterns and vertical adjacent regions between the channel regions, and a semiconductor connecting layer extending from an outer sidewall of the semiconductor pattern to connect the semiconductor pattern to the substrate.

摘要翻译： 提供三维半导体器件。 一种器件包括：电极结构，包括依次层叠在衬底上的导电图案，穿透电极结构的半导体图案，以及包括与导电图案相邻的沟道区域和沟道区域之间的垂直相邻区域;以及从外侧壁延伸的半导体连接层 的半导体图案以将半导体图案连接到基板。

公开(公告)号：US09183893B2

公开(公告)日：2015-11-10

申请号：US14037547

申请日：2013-09-26

申请人： Kohji Kanamori ,  Youngwoo Park ,  Jintaek Park ,  Kwang Soo Seol ,  Jaeduk Lee

发明人： Kohji Kanamori ,  Youngwoo Park ,  Jintaek Park ,  Kwang Soo Seol ,  Jaeduk Lee

IPC分类号： G11C5/06 ,  G11C13/00 ,  H01L45/00 ,  H01L27/22 ,  H01L27/24

CPC分类号： G11C5/06 ,  G11C5/063 ,  G11C13/0002 ,  G11C13/0023 ,  G11C2213/73 ,  H01L27/222 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

摘要： According to example embodiments of inventive concepts, a semiconductor memory devices includes: a plurality of memory blocks that each include a plurality of stack structures, global bit lines connected in common to the plurality of memory blocks, block selection lines configured to control electrical connect between the global bit lines and one of the plurality of memory blocks, and vertical selection lines configured to control electrical connected between the global bit lines and one of the plurality of stack structures. Each of the plurality of stack structures includes a plurality of local bit lines, first vertical word lines and second vertical word lines crossing first sidewalls and second sidewalls respectfully of the plurality of stack structures, first variable resistive elements between the plurality of stack structures and the first vertical word lines, and second variable resistive elements between the plurality of stack structures and the second vertical word lines.

摘要翻译： 根据本发明构思的示例性实施例，半导体存储器件包括：多个存储器块，每个存储块包括多个堆叠结构，共同连接到多个存储器块的全局位线，被配置为控制 全局位线和多个存储器块中的一个以及垂直选择线，其被配置为控制连接在全局位线和多个堆叠结构中的一个之间的电连接。 多个堆叠结构中的每一个包括多个局部位线，第一垂直字线和第二垂直字线，其横向于多个堆叠结构的第一侧壁和第二侧壁相交，多个堆叠结构之间的第一可变电阻元件和 第一垂直字线和第二可变电阻元件在多个堆叠结构和第二垂直字线之间。

公开(公告)号：US08741761B2

公开(公告)日：2014-06-03

申请号：US13165256

申请日：2011-06-21

申请人： Jaegoo Lee ,  Byungkwan You ,  Youngwoo Park ,  Kwang Soo Seol

发明人： Jaegoo Lee ,  Byungkwan You ,  Youngwoo Park ,  Kwang Soo Seol

IPC分类号： H01L23/3205 ,  H01L21/31

CPC分类号： H01L21/3205 ,  H01L27/11578 ,  H01L27/11582

摘要： Methods of manufacturing three-dimensional semiconductor devices that may include forming a first spacer on a sidewall inside a first opening formed in a first stack structure, forming a sacrificial filling pattern on the spacer to fill the first opening, forming a second stack structure including a second opening exposing the sacrificial filling pattern on the first stack structure, forming a second spacer on a sidewall inside the second opening, removing the sacrificial filling pattern and removing the first spacer and the second spacer.

摘要翻译： 制造三维半导体器件的方法，其可以包括在形成在第一堆叠结构中的第一开口内的侧壁上形成第一间隔物，在间隔物上形成牺牲填充图案以填充第一开口，形成第二堆叠结构， 在所述第一堆叠结构上暴露所述牺牲填充图案的第二开口，在所述第二开口内的侧壁上形成第二间隔件，去除所述牺牲填充图案并移除所述第一间隔件和所述第二间隔件。

公开(公告)号：US20110312174A1

公开(公告)日：2011-12-22

申请号：US13165256

申请日：2011-06-21

申请人： Jaegoo Lee ,  Byungkwan You ,  Youngwoo Park ,  Kwang Soo Seol

发明人： Jaegoo Lee ,  Byungkwan You ,  Youngwoo Park ,  Kwang Soo Seol

IPC分类号： H01L21/3205 ,  H01L21/31

CPC分类号： H01L21/3205 ,  H01L27/11578 ,  H01L27/11582

摘要： Methods of manufacturing three-dimensional semiconductor devices that may include forming a first spacer on a sidewall inside a first opening formed in a first stack structure, forming a sacrificial filling pattern on the spacer to fill the first opening, forming a second stack structure including a second opening exposing the sacrificial filling pattern on the first stack structure, forming a second spacer on a sidewall inside the second opening, removing the sacrificial filling pattern and removing the first spacer and the second spacer.

摘要翻译： 制造三维半导体器件的方法，其可以包括在形成在第一堆叠结构中的第一开口内的侧壁上形成第一间隔物，在间隔物上形成牺牲填充图案以填充第一开口，形成第二堆叠结构， 在所述第一堆叠结构上暴露所述牺牲填充图案的第二开口，在所述第二开口内的侧壁上形成第二间隔件，去除所述牺牲填充图案并移除所述第一间隔件和所述第二间隔件。

公开(公告)号：US09478560B2

公开(公告)日：2016-10-25

申请号：US14940137

申请日：2015-11-12

申请人： Kwang Soo Seol ,  JinTae Kang ,  Seong Soon Cho

发明人： Kwang Soo Seol ,  JinTae Kang ,  Seong Soon Cho

IPC分类号： G11C11/34 ,  G11C16/04 ,  H01L27/115 ,  H01L29/792 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L29/06 ,  H01L29/41

CPC分类号： H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/0676 ,  H01L29/413 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/7889 ,  H01L29/7926

摘要： Provided is a memory device including first to third selection lines extending in a first direction and sequentially arranged in a second direction crossing the first direction, multiple sets of first to third vertical pillars, each set coupled with a corresponding one of the first to third selection lines and sequentially arranged in the second direction, a first sub-interconnection connecting the third vertical pillar coupled with the first selection line to the first vertical pillar coupled with the second selection line, a second sub-interconnection connecting the third vertical pillar coupled with the second selection line to the first vertical pillar coupled with the third selection line, and bit lines extending in the second direction and connected to corresponding ones of the first and second sub-interconnections.