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    Semiconductor memory device
    1.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US09183893B2

    公开(公告)日：2015-11-10

    申请号：US14037547

    申请日：2013-09-26

    申请人： Kohji Kanamori ,  Youngwoo Park ,  Jintaek Park ,  Kwang Soo Seol ,  Jaeduk Lee

    发明人： Kohji Kanamori ,  Youngwoo Park ,  Jintaek Park ,  Kwang Soo Seol ,  Jaeduk Lee

    IPC分类号： G11C5/06 ,  G11C13/00 ,  H01L45/00 ,  H01L27/22 ,  H01L27/24

    CPC分类号： G11C5/06 ,  G11C5/063 ,  G11C13/0002 ,  G11C13/0023 ,  G11C2213/73 ,  H01L27/222 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

    摘要： According to example embodiments of inventive concepts, a semiconductor memory devices includes: a plurality of memory blocks that each include a plurality of stack structures, global bit lines connected in common to the plurality of memory blocks, block selection lines configured to control electrical connect between the global bit lines and one of the plurality of memory blocks, and vertical selection lines configured to control electrical connected between the global bit lines and one of the plurality of stack structures. Each of the plurality of stack structures includes a plurality of local bit lines, first vertical word lines and second vertical word lines crossing first sidewalls and second sidewalls respectfully of the plurality of stack structures, first variable resistive elements between the plurality of stack structures and the first vertical word lines, and second variable resistive elements between the plurality of stack structures and the second vertical word lines.

    摘要翻译： 根据本发明构思的示例性实施例，半导体存储器件包括：多个存储器块，每个存储块包括多个堆叠结构，共同连接到多个存储器块的全局位线，被配置为控制 全局位线和多个存储器块中的一个以及垂直选择线，其被配置为控制连接在全局位线和多个堆叠结构中的一个之间的电连接。 多个堆叠结构中的每一个包括多个局部位线，第一垂直字线和第二垂直字线，其横向于多个堆叠结构的第一侧壁和第二侧壁相交，多个堆叠结构之间的第一可变电阻元件和 第一垂直字线和第二可变电阻元件在多个堆叠结构和第二垂直字线之间。

    Three-dimensional semiconductor memory device
    2.
    发明授权
    Three-dimensional semiconductor memory device 有权
    三维半导体存储器件

    公开(公告)号：US08530959B2

    公开(公告)日：2013-09-10

    申请号：US13198234

    申请日：2011-08-04

    申请人： Sung-Il Chang ,  Youngwoo Park ,  Kwang Soo Seol

    发明人： Sung-Il Chang ,  Youngwoo Park ,  Kwang Soo Seol

    IPC分类号： H01L29/78

    CPC分类号： H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

    摘要： Provided are three-dimensional semiconductor devices. A device includes an electrode structure including conductive patterns sequentially stacked on a substrate, a semiconductor pattern penetrating the electrode structure and including channel regions adjacent to the conductive patterns and vertical adjacent regions between the channel regions, and a semiconductor connecting layer extending from an outer sidewall of the semiconductor pattern to connect the semiconductor pattern to the substrate.

    摘要翻译： 提供三维半导体器件。 一种器件包括：电极结构，包括依次层叠在衬底上的导电图案，穿透电极结构的半导体图案，以及包括与导电图案相邻的沟道区域和沟道区域之间的垂直相邻区域;以及从外侧壁延伸的半导体连接层 的半导体图案以将半导体图案连接到基板。

    Non-Volatile Memory Devices Having Reduced Susceptibility to Leakage of Stored Charges and Methods of Forming Same
    3.
    发明申请
    Non-Volatile Memory Devices Having Reduced Susceptibility to Leakage of Stored Charges and Methods of Forming Same 审中-公开
    具有降低存储容量泄漏的易感性的非易失性存储器件及其形成方法

    公开(公告)号：US20110079839A1

    公开(公告)日：2011-04-07

    申请号：US12894863

    申请日：2010-09-30

    申请人： Fayrushin Albert ,  Kwang Soo Seol ,  Jaeduk Lee

    发明人： Fayrushin Albert ,  Kwang Soo Seol ,  Jaeduk Lee

    IPC分类号： H01L29/788

    CPC分类号： H01L29/4234 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/792

    摘要： Provided is a semiconductor device. The semiconductor device includes a substrate, a tunnel insulating layer, a charge storage pattern, a blocking layer, a gate electrode. The tunnel insulating layer is disposed over the substrate. The charge storage pattern is disposed over the tunnel insulating layer. The charge storage pattern has an upper surface, a sidewall, and an edge portion between the upper surface and the sidewall. The blocking layer includes an insulating pattern covering the edge portion of the charge storage pattern, and a gate dielectric layer covering the upper surface, the sidewall, and the edge portion of the charge storage pattern. The gate electrode is disposed over the blocking layer, the gate electrode covering the upper surface, the sidewall, and the edge portion of the charge storage pattern.

    摘要翻译： 提供一种半导体器件。 半导体器件包括衬底，隧道绝缘层，电荷存储图案，阻挡层，栅电极。 隧道绝缘层设置在衬底上。 电荷存储图案设置在隧道绝缘层上。 电荷存储图案具有在上表面和侧壁之间的上表面，侧壁和边缘部分。 阻挡层包括覆盖电荷存储图案的边缘部分的绝缘图案，以及覆盖电荷存储图案的上表面，侧壁和边缘部分的栅极电介质层。 栅电极设置在阻挡层上，栅电极覆盖电荷存储图案的上表面，侧壁和边缘部分。

    Three-dimensional semiconductor memory devices and method of fabricating the same
    5.
    发明授权
    Three-dimensional semiconductor memory devices and method of fabricating the same 有权
    三维半导体存储器件及其制造方法

    公开(公告)号：US09099347B2

    公开(公告)日：2015-08-04

    申请号：US13415388

    申请日：2012-03-08

    申请人： Jang-Gn Yun ,  Kwang Soo Seol ,  Youngwoo Park

    发明人： Jang-Gn Yun ,  Kwang Soo Seol ,  Youngwoo Park

    IPC分类号： H01L29/76 ,  H01L27/115

    CPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

    摘要： Provided are three-dimensional semiconductor memory devices and methods of fabricating the same. The device may include an electrode structure extending in a first direction and including electrodes and insulating patterns which are alternately and repeatedly stacked on a substrate, and vertical active patterns penetrating the electrode structure. At least an uppermost electrode of the electrodes is divided into a plurality of physically isolated segments arranged in the first direction. The segments of the uppermost electrode are electrically connected to each other.

    摘要翻译： 提供三维半导体存储器件及其制造方法。 该器件可以包括在第一方向上延伸的电极结构，并且包括电极和交替重复堆叠在基板上的绝缘图案，以及穿透电极结构的垂直有源图案。 至少电极的最上面的电极被分成沿着第一方向布置的多个物理隔离的部分。 最上面的电极的电极彼此电连接。

    Three-Dimensional Semiconductor Memory Devices and Method of Fabricating the Same
    6.
    发明申请
    Three-Dimensional Semiconductor Memory Devices and Method of Fabricating the Same 有权
    三维半导体存储器件及其制造方法

    公开(公告)号：US20120280299A1

    公开(公告)日：2012-11-08

    申请号：US13415388

    申请日：2012-03-08

    申请人： Jang-Gn Yun ,  Kwang Soo Seol ,  Youngwoo Park

    发明人： Jang-Gn Yun ,  Kwang Soo Seol ,  Youngwoo Park

    IPC分类号： H01L29/68

    CPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

    摘要： Provided are three-dimensional semiconductor memory devices and methods of fabricating the same. The device may include an electrode structure extending in a first direction and including electrodes and insulating patterns which are alternately and repeatedly stacked on a substrate, and vertical active patterns penetrating the electrode structure. At least an uppermost electrode of the electrodes is divided into a plurality of physically isolated segments arranged in the first direction. The segments of the uppermost electrode are electrically connected to each other.

    摘要翻译： 提供三维半导体存储器件及其制造方法。 该器件可以包括在第一方向上延伸的电极结构，并且包括电极和交替重复堆叠在基板上的绝缘图案，以及穿透电极结构的垂直有源图案。 至少电极的最上面的电极被分成沿着第一方向布置的多个物理隔离的部分。 最上面的电极的电极彼此电连接。

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE
    7.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 有权
    三维半导体存储器件

    公开(公告)号：US20120043673A1

    公开(公告)日：2012-02-23

    申请号：US13198234

    申请日：2011-08-04

    申请人： SUNG-IL CHANG ,  Youngwoo Park ,  Kwang Soo Seol

    发明人： SUNG-IL CHANG ,  Youngwoo Park ,  Kwang Soo Seol

    IPC分类号： H01L23/52

    CPC分类号： H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

    摘要： Provided are three-dimensional semiconductor devices. A device includes an electrode structure including conductive patterns sequentially stacked on a substrate, a semiconductor pattern penetrating the electrode structure and including channel regions adjacent to the conductive patterns and vertical adjacent regions between the channel regions, and a semiconductor connecting layer extending from an outer sidewall of the semiconductor pattern to connect the semiconductor pattern to the substrate.

    摘要翻译： 提供三维半导体器件。 一种器件包括：电极结构，包括依次层叠在衬底上的导电图案，穿透电极结构的半导体图案，以及包括与导电图案相邻的沟道区域和沟道区域之间的垂直相邻区域;以及从外侧壁延伸的半导体连接层 的半导体图案以将半导体图案连接到基板。

    Methods of manufacturing three-dimensional semiconductor devices
    8.
    发明授权
    Methods of manufacturing three-dimensional semiconductor devices 有权
    制造三维半导体器件的方法

    公开(公告)号：US08741761B2

    公开(公告)日：2014-06-03

    申请号：US13165256

    申请日：2011-06-21

    申请人： Jaegoo Lee ,  Byungkwan You ,  Youngwoo Park ,  Kwang Soo Seol

    发明人： Jaegoo Lee ,  Byungkwan You ,  Youngwoo Park ,  Kwang Soo Seol

    IPC分类号： H01L23/3205 ,  H01L21/31

    CPC分类号： H01L21/3205 ,  H01L27/11578 ,  H01L27/11582

    摘要： Methods of manufacturing three-dimensional semiconductor devices that may include forming a first spacer on a sidewall inside a first opening formed in a first stack structure, forming a sacrificial filling pattern on the spacer to fill the first opening, forming a second stack structure including a second opening exposing the sacrificial filling pattern on the first stack structure, forming a second spacer on a sidewall inside the second opening, removing the sacrificial filling pattern and removing the first spacer and the second spacer.

    摘要翻译： 制造三维半导体器件的方法，其可以包括在形成在第一堆叠结构中的第一开口内的侧壁上形成第一间隔物，在间隔物上形成牺牲填充图案以填充第一开口，形成第二堆叠结构， 在所述第一堆叠结构上暴露所述牺牲填充图案的第二开口，在所述第二开口内的侧壁上形成第二间隔件，去除所述牺牲填充图案并移除所述第一间隔件和所述第二间隔件。

    Methods Of Manufacturing Three-Dimensional Semiconductor Devices
    10.
    发明申请
    Methods Of Manufacturing Three-Dimensional Semiconductor Devices 有权
    制造三维半导体器件的方法

    公开(公告)号：US20110312174A1

    公开(公告)日：2011-12-22

    申请号：US13165256

    申请日：2011-06-21

    申请人： Jaegoo Lee ,  Byungkwan You ,  Youngwoo Park ,  Kwang Soo Seol

    发明人： Jaegoo Lee ,  Byungkwan You ,  Youngwoo Park ,  Kwang Soo Seol

    IPC分类号： H01L21/3205 ,  H01L21/31

    CPC分类号： H01L21/3205 ,  H01L27/11578 ,  H01L27/11582

    摘要： Methods of manufacturing three-dimensional semiconductor devices that may include forming a first spacer on a sidewall inside a first opening formed in a first stack structure, forming a sacrificial filling pattern on the spacer to fill the first opening, forming a second stack structure including a second opening exposing the sacrificial filling pattern on the first stack structure, forming a second spacer on a sidewall inside the second opening, removing the sacrificial filling pattern and removing the first spacer and the second spacer.

    摘要翻译： 制造三维半导体器件的方法，其可以包括在形成在第一堆叠结构中的第一开口内的侧壁上形成第一间隔物，在间隔物上形成牺牲填充图案以填充第一开口，形成第二堆叠结构， 在所述第一堆叠结构上暴露所述牺牲填充图案的第二开口，在所述第二开口内的侧壁上形成第二间隔件，去除所述牺牲填充图案并移除所述第一间隔件和所述第二间隔件。