公开(公告)号：US5968861A

公开(公告)日：1999-10-19

申请号：US22724

申请日：1998-02-12

申请人： Jennifer S. Feeley ,  Michel Deeba ,  Robert J. Farrauto ,  Dinh Dang

发明人： Jennifer S. Feeley ,  Michel Deeba ,  Robert J. Farrauto ,  Dinh Dang

IPC分类号： B01D53/02 ,  B01D53/86 ,  B01D53/94 ,  B01J29/072 ,  B01J29/46

CPC分类号： B01J29/46 ,  B01D53/9418 ,  B01J29/072 ,  B01D2251/208 ,  B01D2255/20738 ,  B01D2255/20746 ,  B01D2255/20761 ,  B01D2255/504

摘要： A catalytic material useful for the abatement of NO.sub.x in a lean environment containing a zeolite material having incorporated therein copper, cobalt and iron as catalytically active species. The catalytically active metals are preferably incorporated into the zeolite by ion exchange and precipitation. The catalytic material may typically contain from about 2.0 to about 8.0 percent copper, from about 1.0 to about 4.0 percent iron and from about 0.25 to about 4.0 percent cobalt by weight of the catalytic material, i.e., by weight of the zeolite material plus the catalytic metals incorporated therein. Optionally, the catalytic material may be admixed with a binder and applied as an adherent coating onto a carrier to be placed in a gas stream containing the nitrogen oxides.

摘要翻译： 一种催化材料，用于在含有其中掺入有铜，钴和铁作为催化活性物质的沸石材料的稀薄环境中减少NOx。 催化活性金属优选通过离子交换和沉淀引入到沸石中。 催化材料通常可以含有按重量计的催化材料的约2.0至约8.0％的铜，约1.0至约4.0％的铁和约0.25至约4.0％的钴，即以沸石材料的重量加催化剂 并入其中的金属。 任选地，催化材料可以与粘合剂混合并作为粘附涂层施加到载体上以放置在含有氮氧化物的气流中。

公开(公告)号：US5776423A

公开(公告)日：1998-07-07

申请号：US699676

申请日：1996-08-15

申请人： Jennifer S. Feeley ,  Michel Deeba ,  Robert J. Farrauto ,  Dinh Dang

发明人： Jennifer S. Feeley ,  Michel Deeba ,  Robert J. Farrauto ,  Dinh Dang

IPC分类号： B01D53/02 ,  B01D53/86 ,  B01D53/94 ,  B01J29/072 ,  B01J29/46 ,  B01J8/00

CPC分类号： B01J29/46 ,  B01D53/9418 ,  B01J29/072 ,  B01D2251/208 ,  B01D2255/20738 ,  B01D2255/20746 ,  B01D2255/20761 ,  B01D2255/504

摘要： A catalytic material useful for the abatement of NO.sub.X in a lean environment containing a zeolite material having incorporated therein copper, cobalt and iron as catalytically active species. The catalytically active metals are preferably incorporated into the zeolite by ion exchange and precipitation. The catalytic material may typically contain from about 2.0 to about 8.0 percent copper, from about 1.0 to about 4.0 percent iron and from about 0.25 to about 4.0 percent cobalt by weight of the catalytic material, i.e., by weight of the zeolite material plus the catalytic metals incorporated therein. Optionally, the catalytic material may be admixed with a binder and applied as an adherent coating onto a carrier to be placed in a gas stream containing the nitrogen oxides.

摘要翻译： 一种催化材料，其用于在含有其中掺入有铜，钴和铁作为催化活性物质的沸石材料的稀薄环境中减少NOX。 催化活性金属优选通过离子交换和沉淀引入到沸石中。 催化材料通常可以含有按重量计的催化材料的约2.0-约8.0％的铜，约1.0-约4.0％的铁和约0.25-约4.0％的钴，即按沸石材料的重量加催化剂 并入其中的金属。 任选地，催化材料可以与粘合剂混合并作为粘附涂层施加到载体上以放置在含有氮氧化物的气流中。

公开(公告)号：US08674472B2

公开(公告)日：2014-03-18

申请号：US12853532

申请日：2010-08-10

申请人： Alan B. Botula ,  Dinh Dang ,  James S. Dunn ,  Alvin J. Joseph ,  Peter J. Lindgren

发明人： Alan B. Botula ,  Dinh Dang ,  James S. Dunn ,  Alvin J. Joseph ,  Peter J. Lindgren

IPC分类号： H01L21/764

CPC分类号： H01L21/76283 ,  H01L21/76289 ,  H01L27/0738 ,  H01L27/1203 ,  H01L29/0649

摘要： A low harmonic radio-frequency (RF) switch in a silicon-on-insulator (SOI) substrate and methods of manufacture. A method includes forming at least one trench through an insulator layer. The at least one trench is adjacent a device formed in an active region on the insulator layer. The method also includes forming at least one cavity in a substrate under the insulator layer and extending laterally from the at least one trench to underneath the device.

公开(公告)号：US07893479B2

公开(公告)日：2011-02-22

申请号：US12538193

申请日：2009-08-10

申请人： June Cline ,  Dinh Dang ,  Mark Lagerquist ,  Jeffrey C. Maling ,  Lisa Y. Ninomiya ,  Bruce W. Porth ,  Steven M. Shank ,  Jessica A. Trapasso

发明人： June Cline ,  Dinh Dang ,  Mark Lagerquist ,  Jeffrey C. Maling ,  Lisa Y. Ninomiya ,  Bruce W. Porth ,  Steven M. Shank ,  Jessica A. Trapasso

IPC分类号： H01L29/108

CPC分类号： H01L21/31116 ,  H01L21/3081 ,  H01L21/3086 ,  H01L29/66181 ,  Y10S438/952

摘要： A semiconductor structure. A hard mask layer is on a top substrate surface of a semiconductor substrate. The hard mask layer includes a hard mask layer opening through which a portion of the top substrate surface is exposed to a surrounding ambient. The hard mask layer includes a pad oxide layer on the top substrate surface, a nitride layer on the pad oxide layer, a BSG (borosilicate glass) layer on top of the nitride layer, and an ARC (anti-reflective coating) layer on top of the BSG layer. A BSG side wall surface of the BSG layer is exposed to the surrounding ambient through the hard mask layer opening.

摘要翻译： 半导体结构。 硬掩模层位于半导体衬底的顶部衬底表面上。 硬掩模层包括硬掩模层开口，顶部衬底表面的一部分暴露于周围的环境中。 硬掩模层包括在顶部衬底表面上的衬垫氧化物层，衬垫氧化物层上的氮化物层，在氮化物层的顶部上的BSG（硼硅酸盐玻璃）层，以及顶部上的ARC（抗反射涂层） 的BSG层。 BSG层的BSG侧壁表面通过硬掩模层开口暴露于周围环境。

公开(公告)号：US07675121B2

公开(公告)日：2010-03-09

申请号：US11868564

申请日：2007-10-08

申请人： Dinh Dang ,  Thai Doan ,  Jessica Anne Levy ,  Max Gerald Levy ,  Alan Frederick Norris ,  James Albert Slinkman

发明人： Dinh Dang ,  Thai Doan ,  Jessica Anne Levy ,  Max Gerald Levy ,  Alan Frederick Norris ,  James Albert Slinkman

IPC分类号： H01L29/78

CPC分类号： H01L27/1203 ,  H01L21/28518 ,  H01L21/743 ,  H01L21/84

摘要： A low resistance contact structure and method of making the structure. The structure includes a polysilicon contact through an upper silicon layer and buried oxide layer to a lower silicon layer of a silicon-on-insulation substrate. A region of the upper silicon layer surrounds the polysilicon contact and top surface of the polysilicon contact and surrounding region of upper silicon layer are metal silicided providing an extended contact area greater than the area of the top surface of polysilicon contact.

摘要翻译： 低电阻接触结构及其制造方法。 该结构包括通过上硅层和掩埋氧化物层到硅绝缘衬底的下硅层的多晶硅接触。 上硅层的区域围绕多晶硅接触并且多晶硅接触的顶表面和上硅层的周围区域是金属硅化物，提供大于多晶硅接触顶表面的扩展接触面积。

公开(公告)号：US07939896B2

公开(公告)日：2011-05-10

申请号：US12613631

申请日：2009-11-06

申请人： Dinh Dang ,  Thai Doan ,  Jessica Anne Levy ,  Max Gerald Levy ,  Alan Frederick Norris ,  James Albert Slinkman

发明人： Dinh Dang ,  Thai Doan ,  Jessica Anne Levy ,  Max Gerald Levy ,  Alan Frederick Norris ,  James Albert Slinkman

IPC分类号： H01L29/78

CPC分类号： H01L27/1203 ,  H01L21/28518 ,  H01L21/743 ,  H01L21/84

摘要： A low resistance contact structure and method of making the structure. The structure includes a polysilicon contact through an upper silicon layer and buried oxide layer to a lower silicon layer of a silicon-on-insulation substrate. A region of the upper silicon layer surrounds the polysilicon contact and top surface of the polysilicon contact and surrounding region of upper silicon layer are metal silicided providing an extended contact area greater than the area of the top surface of polysilicon contact.

摘要翻译： 低电阻接触结构及其制造方法。 该结构包括通过上硅层和掩埋氧化物层到硅绝缘衬底的下硅层的多晶硅接触。 上硅层的区域围绕多晶硅接触并且多晶硅接触的顶表面和上硅层的周围区域是金属硅化物，提供大于多晶硅接触顶表面的扩展接触面积。

公开(公告)号：US07101806B2

公开(公告)日：2006-09-05

申请号：US10711953

申请日：2004-10-15

申请人： June Cline ,  Dinh Dang ,  Mark Lagerquist ,  Jeffrey C. Maling ,  Lisa Y. Ninomiya ,  Bruce W. Porth ,  Steven M. Shank ,  Jessica A. Trapasso

发明人： June Cline ,  Dinh Dang ,  Mark Lagerquist ,  Jeffrey C. Maling ,  Lisa Y. Ninomiya ,  Bruce W. Porth ,  Steven M. Shank ,  Jessica A. Trapasso

IPC分类号： H01L21/302

CPC分类号： H01L21/31116 ,  H01L21/3081 ,  H01L21/3086 ,  H01L29/66181 ,  Y10S438/952

摘要： A method for etching a deep trench in a semiconductor substrate. The method comprises the steps of (a) forming a hard mask layer on top of the semiconductor substrate, (b) etching a hard mask opening in the hard mask layer so as to expose the semiconductor substrate to the atmosphere through the hard mask layer opening, wherein the step of etching the hard mask opening includes the step of etching a bottom portion of the hard mask opening such that a side wall of the bottom portion of the hard mask opening is substantially vertical, and (c) etching a deep trench in the substrate via the hard mask opening.

摘要翻译： 一种用于蚀刻半导体衬底中的深沟槽的方法。 该方法包括以下步骤：（a）在半导体衬底的顶部上形成硬掩模层，（b）蚀刻硬掩模层中的硬掩模开口，以通过硬掩模层开口将半导体衬底暴露于大气中 其中蚀刻硬掩模开口的步骤包括蚀刻硬掩模开口的底部以使得硬掩模开口的底部的侧壁基本垂直的步骤，以及（c）蚀刻硬掩模开口的底部的深沟槽 基板通过硬掩模开口。

公开(公告)号：US20060081556A1

公开(公告)日：2006-04-20

申请号：US10711953

申请日：2004-10-15

申请人： June Cline ,  Dinh Dang ,  Mark Lagerquist ,  Jeffrey Maling ,  Lisa Ninomiya ,  Bruce Porth ,  Steven Shank ,  Jessica Trapasso

发明人： June Cline ,  Dinh Dang ,  Mark Lagerquist ,  Jeffrey Maling ,  Lisa Ninomiya ,  Bruce Porth ,  Steven Shank ,  Jessica Trapasso

IPC分类号： H01B13/00 ,  B44C1/22

CPC分类号： H01L21/31116 ,  H01L21/3081 ,  H01L21/3086 ,  H01L29/66181 ,  Y10S438/952

摘要： A method for etching a deep trench in a semiconductor substrate. The method comprises the steps of (a) forming a hard mask layer on top of the semiconductor substrate, (b) etching a hard mask opening in the hard mask layer so as to expose the semiconductor substrate to the atmosphere through the hard mask layer opening, wherein the step of etching the hard mask opening includes the step of etching a bottom portion of the hard mask opening such that a side wall of the bottom portion of the hard mask opening is substantially vertical, and (c) etching a deep trench in the substrate via the hard mask opening.

摘要翻译： 一种用于蚀刻半导体衬底中的深沟槽的方法。 该方法包括以下步骤：（a）在半导体衬底的顶部上形成硬掩模层，（b）蚀刻硬掩模层中的硬掩模开口，以通过硬掩模层开口将半导体衬底暴露于大气中 其中蚀刻硬掩模开口的步骤包括蚀刻硬掩模开口的底部以使得硬掩模开口的底部的侧壁基本垂直的步骤，以及（c）蚀刻硬掩模开口的底部的深沟槽 基板通过硬掩模开口。

公开(公告)号：US08912574B2

公开(公告)日：2014-12-16

申请号：US12967771

申请日：2010-12-14

申请人： Mattias E. Dahlstrom ,  Dinh Dang ,  Qizhi Liu ,  Ramana M. Malladi

发明人： Mattias E. Dahlstrom ,  Dinh Dang ,  Qizhi Liu ,  Ramana M. Malladi

IPC分类号： H01L21/763 ,  H01L23/367 ,  H01L21/762 ,  H01L29/08 ,  H01L29/66 ,  H01L29/737

CPC分类号： H01L29/66242 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/763 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/373 ,  H01L29/0821 ,  H01L29/7371 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of making a semiconductor structure includes forming a trench through a shallow trench isolation (STI) structure and into a substrate, and forming a liner including an electrical insulator material on sidewalls of the trench. The method also includes forming a core including a high thermal conductivity material in the trench and on the liner, and forming a cap in the trench and on the core.

摘要翻译： 制造半导体结构的方法包括通过浅沟槽隔离（STI）结构形成沟槽并且形成衬底，以及在沟槽的侧壁上形成包括电绝缘体材料的衬垫。 该方法还包括在沟槽和衬垫上形成包括高导热性材料的芯，并在沟槽和芯上形成帽。

公开(公告)号：US20100084736A1

公开(公告)日：2010-04-08

申请号：US12613631

申请日：2009-11-06

申请人： Dinh Dang ,  Thai Doan ,  Jessica Anne Levy ,  Max Gerald Levy ,  Alan Frederick Norris ,  James Albert Slinkman

发明人： Dinh Dang ,  Thai Doan ,  Jessica Anne Levy ,  Max Gerald Levy ,  Alan Frederick Norris ,  James Albert Slinkman

IPC分类号： H01L29/06

CPC分类号： H01L27/1203 ,  H01L21/28518 ,  H01L21/743 ,  H01L21/84

摘要： A low resistance contact structure and method of making the structure. The structure includes a polysilicon contact through an upper silicon layer and buried oxide layer to a lower silicon layer of a silicon-on-insulation substrate. A region of the upper silicon layer surrounds the polysilicon contact and top surface of the polysilicon contact and surrounding region of upper silicon layer are metal silicided providing an extended contact area greater than the area of the top surface of polysilicon contact.

摘要翻译： 低电阻接触结构及其制造方法。 该结构包括通过上硅层和掩埋氧化物层到硅绝缘衬底的下硅层的多晶硅接触。 上硅层的区域围绕多晶硅接触并且多晶硅接触的顶表面和上硅层的周围区域是金属硅化物，提供大于多晶硅接触顶表面的扩展接触面积。