摘要:
The invention relates to a polarization compensating element (PCE) for a liquid crystal, e.g. liquid crystal on silicon (LCoS), display system manufactured using a linearly photo-polymerizable polymer (LPP) for orienting a photo-polymerizable liquid crystal polymer (LCP) film. To decrease the reflection, polarization conversion, and interference events in an LPP/LCP assembly the ΔN birefringence value of the LCP material is minimized. Dielectric coatings are added at various locations throughout the assembly for minimizing the amount of reflection, polarization conversion, and interference effects and for suppressing spatial retardance ripples.
摘要:
A C-plate compensator is disclosed for compensating the residual A-plate and C-plate retardance of a reflective liquid crystal on silicon (LCoS) display or a transmissive liquid crystal (LC) display in a projection display system. The C-plate incorporates a form-birefringent coating, whose retardance magnitude can be adjusted by tilting with respect to the display panel (X-Y) plane. The tilted plate is rotated about the Z-axis by a prescribed amount from the slow axis of the display panel. Criteria are described for choosing the tilt and rotation angles such that the contrast of the display system produced by the compensated panel is optimized.
摘要:
The present invention relates to trim retarders used to compensate for residual birefringence created by liquid crystal display panels. In particular the present invention relates to a trim retarder with negative out-of-plane birefringence provided by a form birefringent multi-layer dielectric stack for compensating for retardances resulting from liquid crystal on silicon display panels.
摘要:
An oblique angle deposition is used to provide an A-plate optical retarder having at least one dense, form-birefringent layer. According to one embodiment, the dense, form-birefringent layer(s) are deposited as part of an FBAR stack to provide an all-dielectric full-function A/−C-plate trim retarder for LCD birefringence compensation. Advantageously, the dense structure of the full-function A/−C-plate trim retarder offers high durability and/or stability, thus making it well suited for providing polarization compensation in high light flux polarization-based projection systems.
摘要:
A grating trim retarder fabricated from a form-birefringent multi-layer dielectric stack including at least one anti-reflection coating and supported on a transparent substrate is provided. The form-birefringent dielectric stack includes an axially-inhomogeneous element in the form of a −C-plate grating and a transversely-inhomogeneous element in the form of an A-plate grating. Each of the −C-plate and the A-plate gratings are fabricated with dimensions to form a zeroth order sub-wavelength grating structure. Fabricating the grating trim retarder with anti-reflection coatings and/or a segment where the −C-plate and A-plate grating overlap enables the in-plane and out-of-plane retardances to be tailored independently according to the desired application.
摘要:
Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.
摘要:
As part of a process for producing a structured ASIC that is functionally equivalent to an FPGA that has been programmed to perform a user's logic design, a compilation of that design that has been prepared for ASIC implementation is converted to a physical layout of the structured ASIC. The production of this physical layout honors timing constraints supplied by the user, and also preserves functional equivalence to the reference programmed FPGA. The structured ASIC can be manufactured from the physical layout produced.
摘要:
Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.
摘要:
A manufacturing method of a semiconductor device with a copper redistribution line, a copper inductor and aluminum wire bond pads and the integration of the resulting device with an integrated circuit on a single chip, resulting in the decreased size of the chip.