Polarization controlling elements
    1.
    发明申请
    Polarization controlling elements 有权
    极化控制要素

    公开(公告)号:US20050128380A1

    公开(公告)日:2005-06-16

    申请号:US11006379

    申请日:2004-12-07

    摘要: The invention relates to a polarization compensating element (PCE) for a liquid crystal, e.g. liquid crystal on silicon (LCoS), display system manufactured using a linearly photo-polymerizable polymer (LPP) for orienting a photo-polymerizable liquid crystal polymer (LCP) film. To decrease the reflection, polarization conversion, and interference events in an LPP/LCP assembly the ΔN birefringence value of the LCP material is minimized. Dielectric coatings are added at various locations throughout the assembly for minimizing the amount of reflection, polarization conversion, and interference effects and for suppressing spatial retardance ripples.

    摘要翻译: 本发明涉及一种用于液晶的偏振补偿元件(PCE),例如, 硅液晶(LCoS),使用用于取向光聚合性液晶聚合物(LCP)膜的线性光聚合性聚合物(LPP)制造的显示系统。 为了减少LPP / LCP组件中的反射,偏振转换和干涉事件,LCP材料的DeltaN双折射值被最小化。 在整个组件中的各个位置添加介电涂层,以最小化反射量,极化转换和干涉效应以及抑制空间延迟波纹。

    Tilted C-Plate Retarder Compensator And Display Systems Incorporating The Same
    2.
    发明申请
    Tilted C-Plate Retarder Compensator And Display Systems Incorporating The Same 有权
    倾斜的C型板减速器和显示系统结合在一起

    公开(公告)号:US20060268207A1

    公开(公告)日:2006-11-30

    申请号:US11419872

    申请日:2006-05-23

    IPC分类号: G02F1/1335

    摘要: A C-plate compensator is disclosed for compensating the residual A-plate and C-plate retardance of a reflective liquid crystal on silicon (LCoS) display or a transmissive liquid crystal (LC) display in a projection display system. The C-plate incorporates a form-birefringent coating, whose retardance magnitude can be adjusted by tilting with respect to the display panel (X-Y) plane. The tilted plate is rotated about the Z-axis by a prescribed amount from the slow axis of the display panel. Criteria are described for choosing the tilt and rotation angles such that the contrast of the display system produced by the compensated panel is optimized.

    摘要翻译: 公开了用于补偿投影显示系统中的硅(LCoS)显示器或透射型液晶(LC)显示器上的反射液晶的残留A板和C板延迟的C板补偿器。 C板包含双折射形式的涂层,其延迟大小可以通过相对于显示面板(X-Y)平面倾斜来调节。 倾斜板从显示面板的慢轴绕Z轴旋转规定量。 描述了用于选择倾斜和旋转角度的标准,使得由补偿面板产生的显示系统的对比度被优化。

    Thin-Film Optical Retarders
    4.
    发明申请
    Thin-Film Optical Retarders 有权
    薄膜光阻剂

    公开(公告)号:US20070195272A1

    公开(公告)日:2007-08-23

    申请号:US11564500

    申请日:2006-11-29

    IPC分类号: G03B21/14

    摘要: An oblique angle deposition is used to provide an A-plate optical retarder having at least one dense, form-birefringent layer. According to one embodiment, the dense, form-birefringent layer(s) are deposited as part of an FBAR stack to provide an all-dielectric full-function A/−C-plate trim retarder for LCD birefringence compensation. Advantageously, the dense structure of the full-function A/−C-plate trim retarder offers high durability and/or stability, thus making it well suited for providing polarization compensation in high light flux polarization-based projection systems.

    摘要翻译: 使用斜角沉积来提供具有至少一个致密的双折射层的A板光学延迟器。 根据一个实施例,致密的成形双折射层作为FBAR堆叠的一部分沉积,以提供用于LCD双折射补偿的全介质全功能A / -C板修整延迟器。 有利地,全功能A / -C板微调延迟器的致密结构提供高耐久性和/或稳定性,因此使其非常适合于在高光通量极化基投影系统中提供偏振补偿。

    Grating trim retarders
    5.
    发明申请
    Grating trim retarders 有权
    光栅减速器

    公开(公告)号:US20070070276A1

    公开(公告)日:2007-03-29

    申请号:US11591623

    申请日:2006-11-01

    IPC分类号: G02F1/1335

    摘要: A grating trim retarder fabricated from a form-birefringent multi-layer dielectric stack including at least one anti-reflection coating and supported on a transparent substrate is provided. The form-birefringent dielectric stack includes an axially-inhomogeneous element in the form of a −C-plate grating and a transversely-inhomogeneous element in the form of an A-plate grating. Each of the −C-plate and the A-plate gratings are fabricated with dimensions to form a zeroth order sub-wavelength grating structure. Fabricating the grating trim retarder with anti-reflection coatings and/or a segment where the −C-plate and A-plate grating overlap enables the in-plane and out-of-plane retardances to be tailored independently according to the desired application.

    摘要翻译: 提供了由包括至少一个抗反射涂层并且支撑在透明基板上的双折射多层电介质叠层制造的光栅修整延迟器。 形式双折射介质堆叠包括呈-C板格栅形式的轴向不均匀元件和A板格栅形式的横向不均匀的元件。 -C板和A板光栅中的每一个被制造成具有尺寸以形成零级亚波长光栅结构。 制造具有抗反射涂层和/或-C板和A板光栅重叠的光栅调整缓速器可以根据所需的应用独立地调整平面内和平面外的延迟。

    Application-specific integrated circuit equivalents of programmable logic and associated methods
    6.
    发明申请
    Application-specific integrated circuit equivalents of programmable logic and associated methods 有权
    专用集成电路等效的可编程逻辑和相关方法

    公开(公告)号:US20060001444A1

    公开(公告)日:2006-01-05

    申请号:US10884460

    申请日:2004-07-02

    IPC分类号: G06F7/38 H03K19/173 G06F17/50

    CPC分类号: H03K19/177 H03K19/1737

    摘要: Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.

    摘要翻译: 通过使用包括多个所谓的混合逻辑元件(“HLE”)的ASIC架构,提供了ASIC等效的FPGA,使其更加高效和经济,每个ASIC架构可以提供FPGA逻辑元件的全部功能的一部分 (“LE”)。 实现用户逻辑设计的每个FPGA LE的功能可以被映射到一个或多个HLE而不重新合成用户的逻辑。 只有使用必要的HLE才能执行每个LE的功能。 每个LE和(1)一个HLE或(2)一组HLE之间的一对一等价有助于在FPGA和ASIC设计之间的任一方向上的映射(无需重新合成)。

    Methods for producing structured application-specific integrated circuits that are equivalent to field-programmable gate arrays
    7.
    发明申请
    Methods for producing structured application-specific integrated circuits that are equivalent to field-programmable gate arrays 有权
    用于生成与现场可编程门阵列相当的结构化应用专用集成电路的方法

    公开(公告)号:US20060271899A1

    公开(公告)日:2006-11-30

    申请号:US11141941

    申请日:2005-05-31

    申请人: Kim Tan Kar Chua

    发明人: Kim Tan Kar Chua

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5068 G06F2217/64

    摘要: As part of a process for producing a structured ASIC that is functionally equivalent to an FPGA that has been programmed to perform a user's logic design, a compilation of that design that has been prepared for ASIC implementation is converted to a physical layout of the structured ASIC. The production of this physical layout honors timing constraints supplied by the user, and also preserves functional equivalence to the reference programmed FPGA. The structured ASIC can be manufactured from the physical layout produced.

    摘要翻译: 作为生产结构化ASIC的过程的一部分,其功能上等同于已经被编程为执行用户逻辑设计的FPGA,已经为ASIC实现准备的该设计的编译被转换为结构化ASIC的物理布局 。 这种物理布局的生产符合用户提供的时序约束,并且还保留与参考编程FPGA的功能等同性。 结构化ASIC可以从生产的物理布局制造。

    Application-specific integrated circuit equivalents of programmable logic and associated methods
    9.
    发明申请
    Application-specific integrated circuit equivalents of programmable logic and associated methods 有权
    专用集成电路等效的可编程逻辑和相关方法

    公开(公告)号:US20070210827A1

    公开(公告)日:2007-09-13

    申请号:US11801082

    申请日:2007-05-07

    IPC分类号: H03K19/173

    CPC分类号: H03K19/177 H03K19/1737

    摘要: Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.

    摘要翻译: 通过使用包括多个所谓的混合逻辑元件(“HLE”)的ASIC架构,提供了ASIC等效的FPGA,使其更加高效和经济,每个ASIC架构可以提供FPGA逻辑元件的全部功能的一部分 (“LE”)。 实现用户逻辑设计的每个FPGA LE的功能可以被映射到一个或多个HLE而不重新合成用户的逻辑。 只有使用必要的HLE才能执行每个LE的功能。 每个LE和(1)一个HLE或(2)一组HLE之间的一对一等价有助于在FPGA和ASIC设计之间的任一方向上的映射(无需重新合成)。