公开(公告)号：US20120193783A1

公开(公告)日：2012-08-02

申请号：US13341125

申请日：2011-12-30

申请人： Ji-Sun HONG ,  Dae-Young CHOI ,  Mi-Yeon KIM

发明人： Ji-Sun HONG ,  Dae-Young CHOI ,  Mi-Yeon KIM

IPC分类号： H01L23/498 ,  H01L23/522

CPC分类号： H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A package on package is provided herein, the package on package including a first semiconductor package including a first substrate, a first semiconductor chip stacked on the first substrate, a plurality of first connection members on an upper surface of the first substrate and in a first molding material, and a plurality of via holes which respectively expose the plurality of first connection members through the first molding material; a second semiconductor package including a second substrate, a second semiconductor chip stacked on the second substrate, and a plurality of second connection members on a lower surface of the second substrate; and a plurality of connection portions including a plurality of cores and a plurality of conductive fusion layers surrounding the plurality of cores, wherein the plurality of conductive fusion layers contact the upper surface of the first substrate and the lower surface of the second substrate.

摘要翻译： 本文提供了一种封装在封装上的封装，其包装包括第一半导体封装，第一半导体封装包括第一衬底，堆叠在第一衬底上的第一半导体芯片，在第一衬底的上表面上的多个第一连接构件， 模制材料和多个通孔，其分别通过第一模塑材料暴露多个第一连接构件; 第二半导体封装，包括第二衬底，堆叠在第二衬底上的第二半导体芯片和在第二衬底的下表面上的多个第二连接构件; 以及包括多个芯的多个连接部分和围绕所述多个芯的多个导电熔融层，其中所述多个导电熔融层接触所述第一基板的上表面和所述第二基板的下表面。

公开(公告)号：US20120153499A1

公开(公告)日：2012-06-21

申请号：US13244506

申请日：2011-09-25

申请人： Hak-Kyoon BYUN ,  Dae-Young CHOI ,  Mi-Yeon KIM

发明人： Hak-Kyoon BYUN ,  Dae-Young CHOI ,  Mi-Yeon KIM

IPC分类号： H01L23/48

CPC分类号： H01L23/49827 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17179 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package and a package on package are provided. The semiconductor package includes a substrate; a semiconductor chip attached to a surface of the substrate; connecting conductors disposed on the surface of the substrate; a mold formed on the substrate and in which the connecting conductors and the semiconductor chip are provided; and connecting via holes extending through the mold and exposing the connecting conductors. With respect to a first connecting via hole of the connecting via holes, a planar distance between a first connecting conductor exposed by the first connecting via hole and an entrance of the first connecting via hole is not uniform.

摘要翻译： 提供半导体封装和封装封装。 半导体封装包括衬底; 安装在所述基板的表面上的半导体芯片; 设置在基板的表面上的连接导体; 形成在所述基板上并且设置有所述连接导体和所述半导体芯片的模具; 并且连接通过模具延伸的通孔并暴露连接导体。 对于连接通孔的第一连接通孔，由第一连接通孔露出的第一连接导体与第一连接通孔的入口之间的平面距离不均匀。

公开(公告)号：US20120168917A1

公开(公告)日：2012-07-05

申请号：US13279545

申请日：2011-10-24

申请人： Choong-bin YIM ,  Dae-Young CHOI ,  Mi-Yeon KIM ,  Ji-yong PARK

发明人： Choong-bin YIM ,  Dae-Young CHOI ,  Mi-Yeon KIM ,  Ji-yong PARK

IPC分类号： H01L23/495 ,  H01L23/48

CPC分类号： H01L23/49816 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L25/105 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/056 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2402 ,  H01L2224/24051 ,  H01L2224/24105 ,  H01L2224/24226 ,  H01L2224/245 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/82 ,  H01L2224/82105 ,  H01L2225/0651 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/15322 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A stack type semiconductor package and a method of fabricating the stack type semiconductor package. The stack type semiconductor package includes: a lower semiconductor package including a circuit board, a semiconductor chip which is disposed on an upper surface of the circuit board, via-pads which are arrayed on the upper surface of the circuit board around the semiconductor chip, and an encapsulation layer which encapsulates the upper surface of the circuit board and has via-holes through which the via-pads are exposed; and an upper semiconductor package which is stacked on the encapsulation layer, is electrically connected to the lower semiconductor package, and comprises internal connection terminals which are formed on a lower surface of the upper semiconductor package.

摘要翻译： 堆叠型半导体封装以及叠层型半导体封装的制造方法。 叠层型半导体封装包括：下半导体封装，包括电路板，设置在电路板的上表面上的半导体芯片，排列在电路板的上表面周围的半导体芯片的通孔焊盘， 以及封装层，其封装电路板的上表面并具有通孔，通孔穿过该通孔; 并且层叠在封装层上的上半导体封装电连接到下半导体封装，并且包括形成在上半导体封装的下表面上的内部连接端子。