公开(公告)号：US20070218619A1

公开(公告)日：2007-09-20

申请号：US11714850

申请日：2007-03-07

申请人： Ji-hoon Cha ,  Woo-gwam Shim ,  Dong-gyun Han ,  Chang-ki Hong ,  Seung-pil Chung

发明人： Ji-hoon Cha ,  Woo-gwam Shim ,  Dong-gyun Han ,  Chang-ki Hong ,  Seung-pil Chung

IPC分类号： H01L21/8238

CPC分类号： H01L21/76224 ,  Y10S438/954

摘要： A method of manufacturing a nonvolatile semiconductor memory device may include forming a pad oxide layer pattern and a mask pattern on a semiconductor substrate, forming a trench within the semiconductor substrate with the mask pattern functioning as an etching mask, sequentially forming a first device isolation layer and a second device isolation layer that may fill the trench, forming an opening by removing the mask pattern to expose an upper surface of the pad oxide layer pattern and a sidewall of the second device isolation layer, and forming a floating gate forming region having a width wider than the opening by simultaneously removing the pad oxide layer pattern and a sidewall portion of the second device isolation layer exposed by the opening.

摘要翻译： 制造非易失性半导体存储器件的方法可以包括在半导体衬底上形成焊盘氧化物层图案和掩模图案，在半导体衬底内形成沟槽，掩模图案用作蚀刻掩模，顺序地形成第一器件隔离层 以及可以填充沟槽的第二器件隔离层，通过去除掩模图案形成开口以暴露焊盘氧化物层图案的上表面和第二器件隔离层的侧壁，以及形成具有 通过同时去除衬垫氧化物层图案和由开口暴露的第二器件隔离层的侧壁部分，宽度大于开口宽度。

公开(公告)号：US07560386B2

公开(公告)日：2009-07-14

申请号：US11714850

申请日：2007-03-07

申请人： Ji-hoon Cha ,  Woo-gwam Shim ,  Dong-gyun Han ,  Chang-ki Hong ,  Seung-pil Chung

发明人： Ji-hoon Cha ,  Woo-gwam Shim ,  Dong-gyun Han ,  Chang-ki Hong ,  Seung-pil Chung

IPC分类号： H01L21/311

CPC分类号： H01L21/76224 ,  Y10S438/954

摘要： A method of manufacturing a nonvolatile semiconductor memory device may include forming a pad oxide layer pattern and a mask pattern on a semiconductor substrate, forming a trench within the semiconductor substrate with the mask pattern functioning as an etching mask, sequentially forming a first device isolation layer and a second device isolation layer that may fill the trench, forming an opening by removing the mask pattern to expose an upper surface of the pad oxide layer pattern and a sidewall of the second device isolation layer, and forming a floating gate forming region having a width wider than the opening by simultaneously removing the pad oxide layer pattern and a sidewall portion of the second device isolation layer exposed by the opening.

摘要翻译： 制造非易失性半导体存储器件的方法可以包括在半导体衬底上形成焊盘氧化物层图案和掩模图案，在半导体衬底内形成沟槽，掩模图案用作蚀刻掩模，顺序地形成第一器件隔离层 以及可以填充沟槽的第二器件隔离层，通过去除掩模图案形成开口以暴露焊盘氧化物层图案的上表面和第二器件隔离层的侧壁，以及形成具有 通过同时去除衬垫氧化物层图案和由开口暴露的第二器件隔离层的侧壁部分，宽度大于开口宽度。

公开(公告)号：US07745338B2

公开(公告)日：2010-06-29

申请号：US11738155

申请日：2007-04-20

申请人： Ji-hoon Cha ,  Chang-ki Hong ,  Kun-tack Lee ,  Woo-gwan Shim ,  Chang-sup Mun ,  Ho-wook Choi

发明人： Ji-hoon Cha ,  Chang-ki Hong ,  Kun-tack Lee ,  Woo-gwan Shim ,  Chang-sup Mun ,  Ho-wook Choi

IPC分类号： H01L21/311 ,  H01L21/76 ,  H01L21/4763

CPC分类号： H01L21/3086 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3088 ,  H01L21/32139

摘要： A method of forming fine pitch hardmask patterns includes forming a hardmask layer on a substrate and forming a plurality of first mask patterns on the hardmask layer. A buffer layer is formed on the plurality of first mask patterns, and has an upper surface defining recesses between adjacent first mask patterns. Second mask patterns are formed within the recesses formed in the upper surface of the buffer layer. The buffer layer is partially removed to expose upper surfaces of the plurality of first mask patterns, and the buffer layer is then partially removed using the first mask patterns and the second mask patterns as an etch mask to expose the hardmask layer between the first mask pattern and the second mask pattern. Using the first mask patterns and the second mask patterns as an etch mask, the hardmask layer is etched to form hardmask patterns.

摘要翻译： 形成细间距硬掩模图案的方法包括在基底上形成硬掩模层并在硬掩模层上形成多个第一掩模图案。 缓冲层形成在多个第一掩模图案上，并且具有在相邻的第一掩模图案之间限定凹部的上表面。 在形成在缓冲层的上表面中的凹部内形成第二掩模图案。 部分地去除缓冲层以暴露多个第一掩模图案的上表面，然后使用第一掩模图案和第二掩模图案作为蚀刻掩模来部分地去除缓冲层，以在第一掩模图案之间暴露硬掩模层 和第二掩模图案。 使用第一掩模图案和第二掩模图案作为蚀刻掩模，硬掩模层被蚀刻以形成硬掩模图案。

公开(公告)号：US20080014752A1

公开(公告)日：2008-01-17

申请号：US11738155

申请日：2007-04-20

申请人： Ji-hoon Cha ,  Chang-ki Hong ,  Kun-tack Lee ,  Woo-gwan Shim ,  Chang-sup Mun ,  Ho-wook Choi

发明人： Ji-hoon Cha ,  Chang-ki Hong ,  Kun-tack Lee ,  Woo-gwan Shim ,  Chang-sup Mun ,  Ho-wook Choi

IPC分类号： H01L21/311

CPC分类号： H01L21/3086 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3088 ,  H01L21/32139

摘要： A method of forming fine pitch hardmask patterns includes forming a hardmask layer on a substrate and forming a plurality of first mask patterns on the hardmask layer. A buffer layer is formed on the plurality of first mask patterns, and has an upper surface defining recesses between adjacent first mask patterns. Second mask patterns are formed within the recesses formed in the upper surface of the buffer layer. The buffer layer is partially removed to expose upper surfaces of the plurality of first mask patterns, and the buffer layer is then partially removed using the first mask patterns and the second mask patterns as an etch mask to expose the hardmask layer between the first mask pattern and the second mask pattern. Using the first mask patterns and the second mask patterns as an etch mask, the hardmask layer is etched to form hardmask patterns.

摘要翻译： 形成细间距硬掩模图案的方法包括在基底上形成硬掩模层并在硬掩模层上形成多个第一掩模图案。 缓冲层形成在多个第一掩模图案上，并且具有在相邻的第一掩模图案之间限定凹部的上表面。 在形成在缓冲层的上表面中的凹部内形成第二掩模图案。 部分地去除缓冲层以暴露多个第一掩模图案的上表面，然后使用第一掩模图案和第二掩模图案作为蚀刻掩模来部分地去除缓冲层，以在第一掩模图案之间暴露硬掩模层 和第二掩模图案。 使用第一掩模图案和第二掩模图案作为蚀刻掩模，硬掩模层被蚀刻以形成硬掩模图案。

公开(公告)号：US20150162221A1

公开(公告)日：2015-06-11

申请号：US14580513

申请日：2014-12-23

申请人： Hyo-San Lee ,  Chang-ki Hong ,  Kun-tack Lee ,  Jeong-nam Han

发明人： Hyo-San Lee ,  Chang-ki Hong ,  Kun-tack Lee ,  Jeong-nam Han

IPC分类号： H01L21/67 ,  H01J37/32

CPC分类号： H01L21/67017 ,  H01J37/32449 ,  H01J37/32467 ,  H01J37/32715 ,  H01J37/32743 ,  H01J37/32816 ,  H01J2237/334 ,  H01J2237/335 ,  H01L21/67028 ,  H01L21/67069 ,  H01L21/67276 ,  Y10T137/2931 ,  Y10T137/4673

摘要： Provided are an apparatus and method for treating wafers using a supercritical fluid. The wafer treatment apparatus includes a plurality of chambers; a first supply supplying a first fluid in a supercritical state; a second supply supplying a mixture of the first fluid and a second fluid; a plurality of first and second valves; and a controller selecting a first chamber of the plurality of chambers for wafer treatment to control the open/closed state of each of the plurality of first valves so that the first fluid can be supplied only to the first chamber of the plurality of chambers and selecting a second chamber of the plurality of chambers to control the open/closed state of each of the plurality of second valves so that the mixture of the first fluid and a second fluid can be supplied only to the second chamber of the plurality of chambers. The wafer treatment method involves performing a predetermined treatment such as etching, cleaning or drying on wafers within only one of the plurality of chambers, followed by wafer treatment on the succeeding chamber, and thus allowing for sequential wafer treatment within each of the plurality of chambers.

摘要翻译： 提供了一种使用超临界流体处理晶片的设备和方法。 晶片处理装置包括多个室; 供应超临界状态的第一流体的第一供应源; 供应第一流体和第二流体的混合物的第二供应源; 多个第一和第二阀; 以及控制器，选择用于晶片处理的多个室的第一室，以控制多个第一阀中的每一个的打开/关闭状态，使得第一流体仅能够供应到多个室的第一室，并且选择 多个室中的第二室，用于控制多个第二阀中的每一个的打开/关闭状态，使得第一流体和第二流体的混合物只能供应到多个室的第二室。 晶片处理方法包括对多个室内的仅一个中的晶片进行蚀刻，清洗或干燥等预定处理，然后在后续室进行晶片处理，从而允许在多个室内进行顺序晶片处理 。

公开(公告)号：US08030150B2

公开(公告)日：2011-10-04

申请号：US12397543

申请日：2009-03-04

申请人： Byoung-ho Kwon ,  Chang-ki Hong ,  Bo-un Yoon ,  Jun-yong Kim

发明人： Byoung-ho Kwon ,  Chang-ki Hong ,  Bo-un Yoon ,  Jun-yong Kim

IPC分类号： H01L21/8238

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529

摘要： A method of fabricating a non-volatile memory integrated circuit device and a non-volatile memory integrated circuit device fabricated by using the method are provided. A device isolation region is formed in a substrate to define a cell array region and a peripheral circuit region. A plurality of first and second pre-stacked gate structures is formed in the cell array region, and each has a structure in which a lower structure, a conductive pattern and a first sacrificial layer pattern are stacked. Junction regions are formed in the cell array region. Spacers are formed on side walls of the first and second pre-stacked gate structures. A second sacrificial layer pattern filling each space between the second pre-stacked gate structures is formed. The first sacrificial layer pattern is removed from each of the first and second pre-stacked gate structures. A damascene metal layer pattern is formed in each of spaces of the first and second pre-stacked gate structures from which the first sacrificial layer pattern is removed, thus completing first and second stacked gate structures. The second sacrificial layer pattern is removed. A stop layer is formed on top surfaces of the first stacked gate structures, top surfaces and side walls of the second stacked gate structures, and a top surface of the substrate.

摘要翻译： 提供了一种制造使用该方法制造的非易失性存储器集成电路器件和非易失性存储器集成电路器件的方法。 器件隔离区域形成在衬底中以限定电池阵列区域和外围电路区域。 在单元阵列区域中形成多个第一和第二预叠层栅极结构，并且每个都具有堆叠下部结构，导电图案和第一牺牲层图案的结构。 结区域形成在单元阵列区域中。 间隔件形成在第一和第二预堆叠栅极结构的侧壁上。 形成填充第二预堆叠栅极结构之间的每个空间的第二牺牲层图案。 第一牺牲层图案从第一和第二预堆叠栅极结构中的每一个去除。 在第一和第二预堆叠栅极结构的每个空间中形成镶嵌金属层图案，从中去除第一牺牲层图案，从而完成第一和第二堆叠栅极结构。 去除第二牺牲层图案。 在第一层叠栅极结构的顶表面，第二堆叠栅结构的顶表面和侧壁以及衬底的顶表面上形成停止层。

公开(公告)号：US07857939B2

公开(公告)日：2010-12-28

申请号：US11725829

申请日：2007-03-20

申请人： Hyo-san Lee ,  Chang-ki Hong ,  Kun-tack Lee ,  Jeong-nam Han

发明人： Hyo-san Lee ,  Chang-ki Hong ,  Kun-tack Lee ,  Jeong-nam Han

IPC分类号： B67D5/54

CPC分类号： H01L21/67017 ,  H01J37/32449 ,  H01J37/32467 ,  H01J37/32715 ,  H01J37/32743 ,  H01J37/32816 ,  H01J2237/334 ,  H01J2237/335 ,  H01L21/67028 ,  H01L21/67069 ,  H01L21/67276 ,  Y10T137/2931 ,  Y10T137/4673

摘要： Provided are an apparatus and method for treating wafers using a supercritical fluid. The wafer treatment apparatus includes a plurality of chambers; a first supply supplying a first fluid in a supercritical state; a second supply supplying a mixture of the first fluid and a second fluid; a plurality of first and second valves; and a controller selecting a first chamber of the plurality of chambers for wafer treatment to control the open/closed state of each of the plurality of first valves so that the first fluid can be supplied only to the first chamber of the plurality of chambers and selecting a second chamber of the plurality of chambers to control the open/closed state of each of the plurality of second valves so that the mixture of the first fluid and a second fluid can be supplied only to the second chamber of the plurality of chambers. The wafer treatment method involves performing a predetermined treatment such as etching, cleaning or drying on wafers within only one of the plurality of chambers, followed by wafer treatment on the succeeding chamber, and thus allowing for sequential wafer treatment within each of the plurality of chambers.

摘要翻译： 提供了一种使用超临界流体处理晶片的设备和方法。 晶片处理装置包括多个室; 供应超临界状态的第一流体的第一供应源; 供应第一流体和第二流体的混合物的第二供应源; 多个第一和第二阀; 以及控制器，选择用于晶片处理的多个室的第一室，以控制多个第一阀中的每一个的打开/关闭状态，使得第一流体仅能够供应到多个室的第一室，并且选择 多个室中的第二室，用于控制多个第二阀中的每一个的打开/关闭状态，使得第一流体和第二流体的混合物只能供应到多个室的第二室。 晶片处理方法包括对多个室内的仅一个中的晶片进行蚀刻，清洗或干燥等预定处理，然后在后续室进行晶片处理，从而允许在多个室内进行顺序晶片处理 。

公开(公告)号：US20100062548A1

公开(公告)日：2010-03-11

申请号：US12475713

申请日：2009-06-01

申请人： Byoung-ho Kwon ,  Chang-ki Hong ,  Bo-un Yoon ,  Jae-dong Lee ,  Sang-jin Kim

发明人： Byoung-ho Kwon ,  Chang-ki Hong ,  Bo-un Yoon ,  Jae-dong Lee ,  Sang-jin Kim

IPC分类号： H01L21/66 ,  H01L23/544

CPC分类号： H01L23/544 ,  G03F7/70633 ,  G03F9/7076 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A photo key has a plurality of first regions spaced apart from one another on a semiconductor substrate, and a second region surrounding the first regions, and one of the first regions and the second region constitutes a plurality of photo key regions spaced apart from one another. Each of the photo key regions includes a plurality of first conductive patterns spaced apart from one another; and a plurality of second conductive patterns interposed between the first conductive patterns.

摘要翻译： 光钥匙具有在半导体衬底上彼此间隔开的多个第一区域和围绕第一区域的第二区域，并且第一区域和第二区域中的一个构成彼此间隔开的多个光键区域 。 每个照片键区域包括彼此间隔开的多个第一导电图案; 以及介于所述第一导电图案之间的多个第二导电图案。

公开(公告)号：US20090203213A1

公开(公告)日：2009-08-13

申请号：US12219985

申请日：2008-07-31

申请人： Jong-won Lee ,  Chang-ki Hong ,  Sang-yeob Han

发明人： Jong-won Lee ,  Chang-ki Hong ,  Sang-yeob Han

IPC分类号： C09K13/00 ,  H01L21/461

CPC分类号： H01L21/3212 ,  C09G1/02 ,  C09K3/1463

摘要： Provided may be a slurry composition for chemical mechanical polishing (CMP) and a CMP method using the same. For example, the slurry composition may include a first polishing inhibitor including at least one of PO43− or HPO42− and a second polishing inhibitor, which may be a C2-C10 hydrocarbon compound having —SO3H or —OSO3H. By using the slurry composition for CMP and a CMP method using the same, increased selectivity to SiN may be obtained.

摘要翻译： 可提供用于化学机械抛光（CMP）的浆料组合物和使用其的CMP方法。 例如，浆料组合物可以包括第一抛光抑制剂，其包括PO43-或HPO42-和至少一种抛光抑制剂，其可以是具有-SO 3 H或-OSO 3 H的C 2 -C 10烃化合物。 通过使用用于CMP的浆料组合物和使用其的CMP方法，可以获得对SiN的增加的选择性。

公开(公告)号：US20080029159A1

公开(公告)日：2008-02-07

申请号：US11725829

申请日：2007-03-20

申请人： Hyo-san Lee ,  Chang-ki Hong ,  Kun-tack Lee ,  Jeong-nam Han

发明人： Hyo-san Lee ,  Chang-ki Hong ,  Kun-tack Lee ,  Jeong-nam Han

IPC分类号： B67D5/54

CPC分类号： H01L21/67017 ,  H01J37/32449 ,  H01J37/32467 ,  H01J37/32715 ,  H01J37/32743 ,  H01J37/32816 ,  H01J2237/334 ,  H01J2237/335 ,  H01L21/67028 ,  H01L21/67069 ,  H01L21/67276 ,  Y10T137/2931 ,  Y10T137/4673

摘要： Provided are an apparatus and method for treating wafers using a supercritical fluid. The wafer treatment apparatus includes a plurality of chambers; a first supply supplying a first fluid in a supercritical state; a second supply supplying a mixture of the first fluid and a second fluid; a plurality of first and second valves; and a controller selecting a first chamber of the plurality of chambers for wafer treatment to control the open/closed state of each of the plurality of first valves so that the first fluid can be supplied only to the first chamber of the plurality of chambers and selecting a second chamber of the plurality of chambers to control the open/closed state of each of the plurality of second valves so that the mixture of the first fluid and a second fluid can be supplied only to the second chamber of the plurality of chambers. The wafer treatment method involves performing a predetermined treatment such as etching, cleaning or drying on wafers within only one of the plurality of chambers, followed by wafer treatment on the succeeding chamber, and thus allowing for sequential wafer treatment within each of the plurality of chambers.

摘要翻译： 提供了一种使用超临界流体处理晶片的设备和方法。 晶片处理装置包括多个室; 供应超临界状态的第一流体的第一供应源; 供应第一流体和第二流体的混合物的第二供应源; 多个第一和第二阀; 以及控制器，选择用于晶片处理的多个室的第一室，以控制多个第一阀中的每一个的打开/关闭状态，使得第一流体仅能够供应到多个室的第一室，并且选择 多个室中的第二室，用于控制多个第二阀中的每一个的打开/关闭状态，使得第一流体和第二流体的混合物只能供应到多个室的第二室。 晶片处理方法包括对多个室内的仅一个中的晶片进行蚀刻，清洗或干燥等预定处理，然后在后续室进行晶片处理，从而允许在多个室内进行顺序晶片处理 。